公开(公告)号：US12226216B2

公开(公告)日：2025-02-18

申请号：US17412016

申请日：2021-08-25

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang Wu ,  Zhengwu Liu ,  Jianshi Tang ,  Bin Gao ,  He Qian

IPC: G11C13/00 ,  A61B5/00 ,  A61B5/304 ,  A61B5/31

Abstract: A signal processing apparatus and a signal processing method are provided. The signal processing apparatus includes a memristor array, an input circuit, a first switching circuit, a second switching circuit, an output circuit, and a control circuit. The memristor array includes memristor units and is connected to source lines, word lines and bit lines. The control circuit is configured to control the first switching circuit to select at least one source line to apply at least one first signal to the at least one source line respectively, control the second switching circuit to select and activate at least one word line to apply the at least one first signal to a memristor unit corresponding to the at least one word line, and control the output circuit to output a plurality of second signals based on conductivity values of memristors of the memristor array.

公开(公告)号：US11594623B2

公开(公告)日：2023-02-28

申请号：US17058211

申请日：2018-08-03

Applicant: TSINGHUA UNIVERSITY

Inventor： Feng Xu ,  Bin Gao ,  Xinyi Li ,  Huaqiang Wu ,  He Qian

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/417

Abstract: A nanowire transistor and a manufacture method thereof are provided. The nanowire transistor includes a semiconductor wire, a semiconductor layer, a source electrode and a drain electrode. The semiconductor wire includes a first semiconductor material and includes a source region, a drain region, and a channel region, along an axial direction of the semiconductor wire, the channel region is between the source region and the drain region; the semiconductor layer includes a second semiconductor material and covers the channel region of the semiconductor wire; the source electrode is in the source region of the semiconductor wire and is in direct contact with the source region of the semiconductor wire, and the drain electrode is in the drain region of the semiconductor wire and is in direct contact with the drain region of the semiconductor wire.

公开(公告)号：US20210174173A1

公开(公告)日：2021-06-10

申请号：US16071985

申请日：2017-11-14

Applicant: Tsinghua University

Inventor： Xinyi LI ,  Huaqiang Wu ,  Sen SONG ,  Qingtian ZHANG ,  Bin Gao ,  He Qian

IPC: G06N3/063 ,  G06N3/04

Abstract: A circuit structure and a driving method thereof, a neural network are disclosed. The circuit structure includes at least one circuit unit, each circuit unit includes a first group of resistive switching devices and a second group of resistive switching devices, the first group of resistive switching devices includes a resistance gradual-change device, the second group of resistive switching devices includes a resistance abrupt-change device, the first group of resistive switching devices and the second group of resistive switching devices are connected in series, in a case that no voltage is applied, a resistance value of the first group of resistive switching devices is larger than a resistance value of the second group of resistive switching devices. The circuit structure utilizes a resistance gradual-change device and a resistance abrupt-change device connected in series to form a neuron-like structure, so as to achieve to simulate functions of a human brain neuron.

公开(公告)号：US20190074435A1

公开(公告)日：2019-03-07

申请号：US16123234

申请日：2018-09-06

Applicant: Tsinghua University

Inventor： Huaqiang Wu ,  Wei Wu ,  Bin Gao ,  He Qian

IPC: H01L45/00

CPC classification number: H01L45/128 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675

Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

公开(公告)号：US20210049448A1

公开(公告)日：2021-02-18

申请号：US16964435

申请日：2018-02-24

Applicant: Tsinghua University

Inventor： Xinyi LI ,  Huaqiang Wu ,  He Qian ,  Bin Gao ,  Sen Song ,  Qingtian Zhang

IPC: G06N3/06 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: A neural network and its information processing method, information processing system. The neural network includes N layers of neuron layers connected to each other one by one, except for a first layer of neuron layer, each of the neurons of the other neuron layers includes m dendritic units and one hippocampal unit; the dendritic unit includes a resistance value graded device, the hippocampal unit includes a resistance value mutation device, and the m dendritic units can be provided with different threshold voltage or current, respectively; and the neurons on the nth layer neuron layer are connected to the m dendritic units of the neurons on the n+1th layer neuron layer; wherein N is an integer larger than 3, m is an integer larger than 1, n is an integer larger than 1 and less than N.

公开(公告)号：US20210028358A1

公开(公告)日：2021-01-28

申请号：US17037039

申请日：2020-09-29

Applicant: Tsinghua University

Inventor： Huaqiang Wu ,  Wei Wu ,  Bin Gao ,  He Qian

IPC: H01L45/00

Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

公开(公告)号：US20200237311A1

公开(公告)日：2020-07-30

申请号：US16751110

申请日：2020-01-23

Applicant: Tsinghua University

Inventor： Xinyi Li ,  Huaqiang Wu ,  He Qian ,  Bin Gao

IPC: A61B5/00 ,  A61B5/04 ,  A61B5/0488 ,  A61B5/048 ,  G11C13/00

Abstract: A signal processing device and a signal processing method. The signal processing device includes a receiver, a memristor array and a classifier. The receiver is configured to receive a first signal. The memristor array includes a plurality of memristor units, each of the plurality of memristor units includes a memristor, and the memristor array is configured to apply the first signal that has been received to at least one memristor unit of the plurality of memristor units and output a second signal based on a memristor resistance value distribution of the memristor array. The classifier is configured to classify the second signal outputted from the memristor array to obtain a type of the first signal.

公开(公告)号：US10475512B2

公开(公告)日：2019-11-12

申请号：US15776520

申请日：2016-12-22

Applicant: Tsinghua University

Inventor： Chen Wang ,  Huaqiang Wu ,  He Qian ,  Bin Gao

IPC: G11C11/00 ,  G11C13/00

Abstract: An operation method of a resistance random access memory and a resistance random access memory apparatus are provided. The method includes: applying an initial reset voltage to a storage unit; carrying out a read check operation to acquire a resistance value of the storage unit; judging whether the resistance value of the storage unit reaches a preset target resistance value in a high resistance state; if the resistance value of the storage unit is less than the preset target resistance value in the high resistance state, applying a set voltage to the storage unit to set the storage unit to a preset target resistance value in a low resistance state, then applying a reset voltage of which an amount is increased to the storage unit, and repeating the read check operation and the subsequent steps until the storage unit reaches the preset target resistance value in the high resistance state.

公开(公告)号：US10468099B2

公开(公告)日：2019-11-05

申请号：US16132931

申请日：2018-09-17

Applicant: Tsinghua University

Inventor： Huaqiang Wu ,  Yachuan Pang ,  Bin Gao ,  He Qian

IPC: G11C11/00 ,  G11C13/00 ,  H04L9/32 ,  H01L27/24 ,  G09C1/00

Abstract: A circuit structure for implementing a physical unclonable function and a driving method thereof, an integrated circuit chip and an authentication method thereof, an electronic device are disclosed. The circuit structure includes: a multilayer circuit, a first address circuit and an output circuit, the multilayer circuit includes a first RRAM device array which is addressable and a second RRAM device array which is addressable; the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address; the first address is used for positioning a selected first RRAM device; and the output circuit is configured to acquire and process a resistance value of the selected first RRAM device and output a processing result.

公开(公告)号：US11468300B2

公开(公告)日：2022-10-11

申请号：US16071985

申请日：2017-11-14

Applicant: Tsinghua University

Inventor： Xinyi Li ,  Huaqiang Wu ,  Sen Song ,  Qingtian Zhang ,  Bin Gao ,  He Qian

IPC: G06N3/063 ,  G06N3/04

Abstract: A circuit structure and a driving method thereof, a neural network are disclosed. The circuit structure includes at least one circuit unit, each circuit unit includes a first group of resistive switching devices and a second group of resistive switching devices, the first group of resistive switching devices includes a resistance gradual-change device, the second group of resistive switching devices includes a resistance abrupt-change device, the first group of resistive switching devices and the second group of resistive switching devices are connected in series, in a case that no voltage is applied, a resistance value of the first group of resistive switching devices is larger than a resistance value of the second group of resistive switching devices.