公开(公告)号：JPH10135428A

公开(公告)日：1998-05-22

申请号：JP14045897

申请日：1997-05-29

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device having a tree-type capacitor structure having increased regions for storing charge. SOLUTION: A field oxide film 12 is formed on the surface of an Si substrate 10, a polysilicon layer is deposited on the entire surface to form a polycide, and gate electrodes WL1-WL4, drain regions 16a, 16b and source regions 18a, 18b are formed to deposit an insulating layer 20. An etch protect layer 22, planarizing insulating film 20 and gate oxide layer 14 are etched, an insulating film 34, polysilicon layer 32, insulating layer 30 and polysilicon layer 26 are etched to form openings, dielectric films 40a, 40b are formed on the surfaces of storage electrodes 26a, 32a, 38a; 26b, 32b, 38b. Opposed polysilicon electrodes 42 are formed on the surfaces of dielectric film 40a, 40b to form storage capacitors of a DRAM.

公开(公告)号：JPH1079489A

公开(公告)日：1998-03-24

申请号：JP7776697

申请日：1997-03-28

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To widen a charge storage area by forming a transfer transistor on a substrate and electrically connecting one of the source/drain regions of the transfer transistor to a charge storage capacitor. SOLUTION: A storage electrode of a charge storage capacitor in a DRAM has trunk-polysilicon layers 26a, 26b and branch polysilicon layers 40a, 40b, each having an L-shape in cross section. The trunk-polysilicon layers 26a, 26b, each having a T-letter shape in cross section, are electrically connected to drain regions 16a, 16b of a transfer transistor in the DRAM, respectively. Each of the branch-polysilicon layers 40a, 40b generally has a hollow cylindrical shape and its horizontal cross section may be circular, rectangular, or the like according to the shape of each of deposition layers 30a, 32a, and 30b, 32b. The branch polysilicon layers 40a, 40b extend vertically upward from the top face of the trunk polysilicon layers 26a, 26b and then extend outwardly in the horizontal direction.

公开(公告)号：JPH1079488A

公开(公告)日：1998-03-24

申请号：JP795097

申请日：1997-01-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To widen a charge storage area by allowing a branch conductive layer having an end connected to an almost vertical trunk conductive layer connected to a drain region of a transfer transistor to have a wide surface and by forming an overlay conductive layer on a dielectric layer formed on an exposed face of each of the conductive layers. SOLUTION: Trunk-polysilicon layers 26a, 26b are connected to drain regions 16a, 16b of a transfer transistor, respectively. The intermediate part of each of upper-branch polysilicon layers 34a, 34b is connected to the upper end of each of the trunk-polysilicon layers 26a, 26b and is arranged at an almost right angle to the polysilicon layer. Substantially L-type and branch polysilicon layers 30a, 30b extend downward from the under face of the upper branch polysilicon layers 34a, 34b and then extend horizontally. Dielectric films 36a, 36b are formed on the tree-type storage electrodes 26a, 30a, 34a and 26b, 30b, 34b, and a polysilicon counter electrode 38 facing the electrodes is formed on the dielectric films 36a, 36b.

公开(公告)号：JPH1079487A

公开(公告)日：1998-03-24

申请号：JP794997

申请日：1997-01-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To widen a charge storage area by widening the surface of a branch conductive layer connected to an almost vertical trunk conductive layer, connected to a drain region of a transfer transistor and by forming an overlay conductive layer on a dielectric layer formed on an exposed face of both of the conductive layers. SOLUTION: Trunk-polysilicon layers 26a, 26b are electrically connected to drain regions 16a, 16b of a transfer transistor in a DRAM, respectively. The intermediate part of each of upper branch polysilicon layers 34a, 34b is connected to the upper end of each of the trunk-polysilicon layers 26a, 26b and is arranged at almost a right angle to the polysilicon layer. Branch polysilicon layers 30a, 30b extend downward from the under faces of the upper branch polysilicon layers 34a, 34b and then extend horizontally. Dielectric films 36a, 36b are formed on the tree-type storage electrodes 26a, 30a, 34a and 26b, 30b, 34b, and a polysilicon counter electrode 38 is formed on the dielectric films 36a, 36b.

公开(公告)号：JPH1079476A

公开(公告)日：1998-03-24

申请号：JP9117997

申请日：1997-04-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor memory device, having a tree type capacitor structure capable of widening the memory electrode area, without widening the surface area of the used semiconductor memory device. SOLUTION: A dielectric layer 46 made of, e.g. silicon dioxide, silicon nitride, No or ONO, is formed on the entire exposed surfaces of a trunk-like polysilicon layer 44A and section 38 of a branch-like polysilicon layer. To complete manufacturing of a tree-type capacitor, a polysilicon layer 48 functioning as counter- electrodes to the memory electrodes 44A, 38 is formed on the entire dielectric layer 46. The process of forming the electrode 48 includes a first step of vacuum evaporation to, e.g. a depth of about 1000Å, a 2nd step of diffusing an n-type impurity in the polysilicon layer for raising the conductivity, and etching the polysilicon layer to form the desired oppositely located electrodes 48.

公开(公告)号：JPH1079474A

公开(公告)日：1998-03-24

申请号：JP7760397

申请日：1997-03-28

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To increase a charge storage area by providing source and drain regions on a substrate, a transfer transistor on the substrate, and a charge storage capacitor electrically connected to one of the source and drain regions of the transfer transistor. SOLUTION: Storage electrodes respectively have trunk-shaped polysilicon layers 26a and 26b and branch-shaped polysilicon layers 40a and 40b respectively, having an L-shaped cross section. The trunk-shaped polysilicon layers 26a and 26b are electrically connected to drain regions 16a and 16b of the transfer transistor in a DRAM, thus respectively forming a T-shaped cross section. The branch-shaped polysilicon layers 40a and 40b extend vertically upward from the upper surfaces of the trunk-shaped polysilicon layers 26a and 26b by a predetermined distance, then extend in a horizontal direction toward the outside. Dielectric films 42a and 42b are formed the entire exposed surfaces of the storage electrodes 26a, 40a, and 26b and 40b, and a polysilicon oppositely located electrode 44 is formed on the surfaces of the dielectric films 42a and 42b.

公开(公告)号：JPH11220097A

公开(公告)日：1999-08-10

申请号：JP32639898

申请日：1998-11-17

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING ,  SHA BUNEKI ,  KO KOKUTAI

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a capacitor in a dynamic RAM, by changing a first tantalum oxide layer to a first acid tantalum nitride layer due to RTA treatment, and by forming a second acid tantalum nitride layer being formed on the first tantalum nitride layer on a second tantalum oxide layer. SOLUTION: A first tantalum oxide layer is formed on a polysilicon layer 30 being used as a lower electrode, first rapid thermal anneal treatment is made in ammonia atmosphere, and a first tantalum nitride layer 32a is formed by the reaction between the first tantalum oxide layer and ammonium. A second tantalum oxide layer is formed on a first acid tantalum nitride layer 32a, second rapid thermal anneal treatment is executed in dinitrogen monoxide atmosphere to rearrange the atom of a second tantalum oxide layer, third rapid thermal anneal treatment is executed in the ammonium atmosphere, and second tantalum nitride 36 is formed on the second tantalum oxide layer. After that, an upper electrode 38 is formed on the acid tantalum nitride layer 36.

公开(公告)号：JPH1079490A

公开(公告)日：1998-03-24

申请号：JP9118097

申请日：1997-04-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To widen a charge storage area, without widening the surface of a substrate in such a manner that a trunk conductive member of a charge storage capacitor connected to a transfer transistor has lower and upper trunk layers and an L-letter shaped branch conductive layer is connected to the upper trunk layer. SOLUTION: A first storage electrode 49a and a second storage electrode 49b of a DRAM storage capacitor have lower trunk-polysilicon layers 26a, 26b, upper trunk-polysilicon layers 46a, 46b, and branch polysilicon layers 40a, 40b, respectively. Each of the branch polysilicon layers 40a, 40b has L-shape cross section and has a vertical expanding part which extends toward a top face 11 of a substrate 10 and a horizontal extension part which is in direct contact with the inner face of each of the trunk upper polysilicon layers 46a, 46b. The lower trunk polysilicon layers 26a, 26b, each having a T-shape cross section are in direct contact with drain regions 16a, 16b of the DRAM transfer transistor, respectively.

公开(公告)号：JPH1079475A

公开(公告)日：1998-03-24

申请号：JP9117897

申请日：1997-04-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To increase a charge storage area by providing a transfer transistor having source and drain regions, formed on a substrate, and a tree-type capacitor electrically connected to one of the source and drain regions of the transfer transistor. SOLUTION: A storage electrode has a trunk-shaped polysilicon layer 44, having a substantially T-shaped cross section and a branch-shaped polysilicon layer 38 having a substantially L-shaped cross section. The bottom of the trunk- shape polysilicon layer 44 is electrically connected to a drain region 16 of the transfer transistor of the DRAM cell. Sections of the branch-shaped polysilicon layer 38 extend sideward from a vertical portion and extend downward toward a substrate 10. Next, a dielectric layer 46 is formed over the entire exposed surfaces of the trunk-shaped polysilicon layer 44 and the sections of the branch shaped polysilicon layer 38. Next, a polysilicon layer 48 as an oppositely located electrode to the storage electrodes 44 and 38 is formed over the entire dielectric layer 46.

公开(公告)号：JPH1079486A

公开(公告)日：1998-03-24

申请号：JP508797

申请日：1997-01-14

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for semiconductor memory elements having wide-area tree-type capacitors for storing of data-representing charges. SOLUTION: On an Si substrate 10 a field oxide film and gate oxide film are formed. By the CVD a poly-Si film is formed, W is vacuum-evaporated and heat treated to form a low-resistance silicide film, which is then patterned to form gate electrodes WL1-WL4. Using these electrodes as a mask, P ions are implanted and diffused to form drain regions 16a, 16b and source regions 18a, 18b. A BPSG film 20 and SiN etching protection layer 22 are formed. A first insulation layer, poly-Si layers 28a, 28b and a second insulation layer are formed by the CVD. The poly-Si layer top is treated by CMP to separate into numerous independent sections. Each of the above layers is etched to form connecting holes up to the drain/source region, and poly-Si 34a, 34b are filled in the connecting holes. Tree-type memory electrodes for DRAM capacitors are formed, and dielectric counter films 36a, 36b and poly-Si facing electrodes 38 are vacuum-evaporated to complete the element.