公开(公告)号：JPH11220097A

公开(公告)日：1999-08-10

申请号：JP32639898

申请日：1998-11-17

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING ,  SHA BUNEKI ,  KO KOKUTAI

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a capacitor in a dynamic RAM, by changing a first tantalum oxide layer to a first acid tantalum nitride layer due to RTA treatment, and by forming a second acid tantalum nitride layer being formed on the first tantalum nitride layer on a second tantalum oxide layer. SOLUTION: A first tantalum oxide layer is formed on a polysilicon layer 30 being used as a lower electrode, first rapid thermal anneal treatment is made in ammonia atmosphere, and a first tantalum nitride layer 32a is formed by the reaction between the first tantalum oxide layer and ammonium. A second tantalum oxide layer is formed on a first acid tantalum nitride layer 32a, second rapid thermal anneal treatment is executed in dinitrogen monoxide atmosphere to rearrange the atom of a second tantalum oxide layer, third rapid thermal anneal treatment is executed in the ammonium atmosphere, and second tantalum nitride 36 is formed on the second tantalum oxide layer. After that, an upper electrode 38 is formed on the acid tantalum nitride layer 36.

公开(公告)号：JPH11307738A

公开(公告)日：1999-11-05

申请号：JP23905598

申请日：1998-08-25

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  SHA BUNEKI ,  YEW TRI-RUNG

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To form a plurality of gates, a common source/drain region and a source/drain region on a substrate by a method wherein a self-alignment contact window to be opened (hereinafter, a PSACW) is formed and a part of the common source/drain region is exposed. SOLUTION: After a source/drain 210 and a common source/drain region 210a are sufficiently formed, an insulation film 212 is formed on a substrate 200 and a gate 202. By using self-alignment technology, a PSACW 211 is formed in the insulation film 212, which becomes an insulation film 202a. By using this technology in order to form a PASCW 211, an etching process can be simply performed and a manufacture can be simplified more. Further, a sidewall having the inclined PACW 211 is provided with a larger region, and the PASCW can store greater electric charges.

公开(公告)号：JP2000307076A

公开(公告)日：2000-11-02

申请号：JP11200099

申请日：1999-04-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN KAKUKI ,  KO KOKUTAI ,  KA DAIBUN ,  RIN KONKICHI

IPC: H01L27/04 ,  H01L21/205 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To avoid degassing and improve the quality of a hemispheric particle by forming a conductor layer that is subjected to pattern formation on one portion of a suppression layer and burying a node contact hole and then forming a selective hemispheric particle layer on the conductor layer that is subjected to pattern formation. SOLUTION: A dielectric layer 214, a cap layer 212, and a dielectric layer 210 are subjected to patterning for forming a node contact hole 216, and then a conformal layer 218 is formed on the dielectric layer 214. Further, when the conformal layer 218 is to be eliminated partially, an etching gas is allowed to react with the surface of the dielectric layer 214 and a suppression layer 222 is formed on the dielectric layer 214. Then, a conductor layer 224 that is subjected to pattern formation is formed on the suppression layer 222 so that the node contact hole 216 can be buried, and at the same time a selective hemispheric particle layer 226 is formed on the conductive layer 224.

公开(公告)号：JP2000208736A

公开(公告)日：2000-07-28

申请号：JP815899

申请日：1999-01-14

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHU SHIKUN ,  CHIN KONAN ,  RIN KAKUKI ,  KO KOKUTAI ,  SHA BUNEKI ,  YU SUIYO

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/203 ,  H01L21/768 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To shorten the time required for manufacturing the lower electrode in a DRAM capacitor. SOLUTION: In this method for manufacturing the lower electrode in a DRAM capacitor, a polysilicon is vapor-deposited in place of an amorphous silicon to manufacture a lower electrode 250b. The vapor-deposition temperature of the polysilicon is higher than that for amorphous silicon, so that the vapor- deposition rate of the polysilicon becomes higher than that of amorphous silicon and its vapor-deposition time is shortened greatly. After the formation of polysilicon lower electrode, an ion group 270 is bombarded on a polysilicon layer to destroy the inner structure of the polysilicon layer, so as to change the upper part thereof into an amorphous silicon layer 252a. Finally, by forming a semispherical grain silicon 290 on the lower electrode, the surface area of the lower electrode is increased.

公开(公告)号：JP2001044385A

公开(公告)日：2001-02-16

申请号：JP21098599

申请日：1999-07-26

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  YEW TRI-RUNG

IPC: H01L21/26 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a DRAM capacitor dielectric film having superior dielectric constant. SOLUTION: After a ditantalum pentoxide dielectric film 104 is deposited on a surface of a polysilicon accumulating electrode 102, is the ditantalum pentoxide dielectric film is subjected to two-stage process, and first a remote oxygen plasma process or an UV-ray ozone process is carried out, and next a spike annealing process is carried out. Thus, when the ditantalum pentoxide dielectric film is subjected to two-stage process, the first stage remote oxygen plasma is emitted at relatively lower temperature, and also as the required time of a second stage spike annealing process is extremely short, a thermal history of a manufacture process of a dielectric film can be reduced.

公开(公告)号：JP2000340762A

公开(公告)日：2000-12-08

申请号：JP13983299

申请日：1999-05-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  YEW TRI-RUNG ,  RO KATETSU

IPC: H01L27/04 ,  H01L21/265 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing the storage node for a capacitor. SOLUTION: After an insulating layer 108 is formed on a substrate 100, and is subjected to an ion-implantation step. Then, the insulating layer is patterned to provide an opening 112 which is exposed as a part of the substrate on the insulating layer 108, and a patterned conductor layer 114 is so formed as to fill the opening on the insulating layer, forming a hemispherical Si particle layer on the conductor layer. The order, in which the ion-implantation step is performed, may be changed as required. In this case, the opening for exposing a part of the substrate is provided at the insulating layer, before being subjected to ion-implantation.

公开(公告)号：JP2000091538A

公开(公告)日：2000-03-31

申请号：JP32102298

申请日：1998-11-11

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  SHA BUNEKI ,  YEW TRI-RUNG

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a more simplified manufacturing method by using tungsten nitride as an MIM(metal-insulator-metal) capacitor structure. SOLUTION: In the process of forming a DRAM capacitor, a tungsten nitride is used. A step for introducing nitrogen to a tungsten silicide layer 110b and the step for performing rapid heat processing in the presence of ammonia gas, so as to form a tungsten nitride layer 111 on the surface of the tungsten silicide layer 110b are provided. This manufacturing method is provided with the formation of the tungsten silicide layer 110b, after forming a part smaller than the bottom electrode of the capacitor from doped polysilicon and the formation of the tungsten nitride on the surface of the tungsten nitride layer 111.

公开(公告)号：JPH11191612A

公开(公告)日：1999-07-13

申请号：JP7378098

申请日：1998-03-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  SHA BUNEKI ,  YO BUNKAN ,  YEW TRI-RUNG

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To prevent the generation of leakage current in a capacitor by implanting a silicon layer with ions for converting it into a barrier layer and then forming a dielectric layer on the barrier layer after heat treatment and wet etching thereby, improving the quality of the dielectric layer. SOLUTION: An HSG layer 32 is formed on the surface of a conductive layer 30 using SiH4 and Si2 H6 as reaction gases, for example, and implanted with nitrogen ions. Thereafter, a thin barrier layer 34 of silicon oxynitride or silicon nitride, for example, is formed on the HSG layer 32 through rapid heating process. Since a thin native oxide layer 33 is formed on the surface of the barrier layer 34, this is removed through wet etching process. Subsequently, a dielectric layer 36 of tantalum oxide is formed on the surface of the battier layer 34 by LPCVD, followed by the formation of a top electrode layer 38 of titanium nitride on the surface of the dielectric layer 36.

公开(公告)号：JP2001085423A

公开(公告)日：2001-03-30

申请号：JP25637999

申请日：1999-09-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  YEW TRI-RUNG

IPC: H01G4/10 ,  C23C16/40 ,  H01G4/33 ,  H01L21/31 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a desired capacitance by using a tantalum-contained organic compound and titanium-contained organic compound as a precursor for organic metal chemical vapor-phase deposition, to form a dielectric layer. SOLUTION: A tantalum-contained organic compound, such as tantalum pentaethoxide, tantalum tetraxy dimethylaminoethoxide, tantalum tetramethoxy tetramethylheptanedionate, as well as a titanium-contained organic compound selected out of titanium diethoxy bidimethylaminoetoxide, titanium tetrakis-t- butoxide are used as a precursor (200), to perform an organic metal chemical vapor-phase deposition stage (210), forming a tantalum titanic oxide dielectric layer as a single phase. Thus, a desired capacitance is provided.

公开(公告)号：JP2001023923A

公开(公告)日：2001-01-26

申请号：JP19410299

申请日：1999-07-08

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  KO KOKUTAI ,  RO KATETSU

IPC: H01L23/52 ,  H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To prevent the increase of the contact resistance of a contact pad, even when the positional discrepancy of a node contact hole occurs, by forming in a dielectric layer an opening to expose to it a source/drain region, and by extending out on the top surface of the dielectric layer the upper portion of the contact pad. SOLUTION: A shallow-trench insulation structure 320 is formed in a substrate 300, gate structures 306 are formed on the substrate 300, source/drain regions 304 are formed in the exposed portions of the substrate 300 by the gate structures 306, and a dielectric layer 308 made of silicon oxide is formed on the substrate 300 by a chemical vapor deposition method. While a contact pad 312 is formed in an opening 310 after forming in the dielectric layer 308 the opening 310 to expose to it a portion of the source/drain region 304, the contact pad 312 is so formed that its upper portion is extended out on the flat top surface of the dielectric layer 308. For example, as the material of the contact pad 312, polysilicon is used preferably.