公开(公告)号：JPH11330417A

公开(公告)日：1999-11-30

申请号：JP20805398

申请日：1998-07-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN EISHO

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To prevent a shallow PN junction between a source/drain region and a substrate from being made still thinner by a self-aligned silicide process. SOLUTION: An SEG process is carried out for forming plural amorphous silicon layers on polycrystalline silicon for various FETs and source/drain regions. A self-aligned silicide process is carried out on the layers to form titanium silicide layers 344, 346, 348 and 350, and the titanium silicide layers 344, 346, 348 and 350 are spaced from the substrate by source/drain regions. Since the formation of the titanium silicide layers 344, 346, 348 and 350 does not deplete the silicon atoms part of a substrate 300, shallow junctions causing leakage current in a DRAM device are prevented from being still thinner. In the case of a dual gate complementary metal oxide semiconductor(CMOS) structure, since the silicide layers are formed after the activation of impurities in the source/drain regions generation of mutual diffusion effect between an N-type polycrystalline silicon layer and a P-type polycrystal silicon layer can be prevented.

公开(公告)号：JP2000150797A

公开(公告)日：2000-05-30

申请号：JP32480798

申请日：1998-11-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN EISHO ,  CHIN TOHA ,  CHIN SHIKI

IPC: H01L21/822 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To prevent the interlayer diffusion between two regions of different doping types of a gate structure by forming a self-alignment silicide compound on first mutual exchange source/drain regions and the exposed top surface of first and second polysilicon gate structures. SOLUTION: An insulation layer 212a on a substrate 200 for covering both of first and second MOS transistors is formed, and the top portion of the insulation layer 212a is eliminated to expose the top portion of first and second gate structures. Also, one portion of an insulation layer 212b for covering the first MOS transistor is eliminated to expose the first MOS transistor. Then, using the remaining insulation layer 212b on the second MOS transistor as a mask, a self-alignment silicide compound layer 224 is formed on first source/drain regions 229 that exchange each other and on the exposed top surface of the first and second polysilicon gate structures.