公开(公告)号：JP2000150797A

公开(公告)日：2000-05-30

申请号：JP32480798

申请日：1998-11-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN EISHO ,  CHIN TOHA ,  CHIN SHIKI

IPC: H01L21/822 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To prevent the interlayer diffusion between two regions of different doping types of a gate structure by forming a self-alignment silicide compound on first mutual exchange source/drain regions and the exposed top surface of first and second polysilicon gate structures. SOLUTION: An insulation layer 212a on a substrate 200 for covering both of first and second MOS transistors is formed, and the top portion of the insulation layer 212a is eliminated to expose the top portion of first and second gate structures. Also, one portion of an insulation layer 212b for covering the first MOS transistor is eliminated to expose the first MOS transistor. Then, using the remaining insulation layer 212b on the second MOS transistor as a mask, a self-alignment silicide compound layer 224 is formed on first source/drain regions 229 that exchange each other and on the exposed top surface of the first and second polysilicon gate structures.

公开(公告)号：JPH11191615A

公开(公告)日：1999-07-13

申请号：JP7806298

申请日：1998-03-25

Applicant: UNITED MICROELECTRONICS CORP

Inventor： WU H J ,  SUN SHIH-WEI ,  CHIN SHIKI ,  YEW TRI-RUNG

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To form an integrated circuit device having respective arrays of a logic circuit and an embedded DRAM, while avoiding low yield. SOLUTION: A transfer FET 104 and a wiring line 106 are provided on an embedded DRAM circuit in the prestage of a process, while a logic FET 120 is provided on a logic circuit part. A gate electrode and source/drain regions of the logic 120 are made salicide in the initial stage, and a thick and planarized oxide layer is provided on the device. Next, a capacitor and a logic wiring are formed through the use of common etching, titanium nitride deposition and tungsten deposition steps. Then, in order to expose source/drain regions of the transfer FET 104, a contact via is formed. A titanium nitride layer is deposited on the device and in the contact via. Furthermore, after the selective removal of a capacitor dielectric layer provided on the device, a tungsten layer is pattern-formed to complete an upper capacitor electrode 158, a bit-line contact 160, and a logic circuit wiring 162.