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    Dual damascene technique
    3.
    发明专利
    Dual damascene technique 未知

    公开(公告)号：GB2340657A

    公开(公告)日：2000-02-23

    申请号：GB9812531

    申请日：1998-06-10

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： TSAI MENG-JIN

    IPC: H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768

    Abstract: The method comprises depositing, onto a substrate 50 which has conductive layers 54, a first oxide layer 56 which has protruding portions formed above the conductive layers 54. A mask layer 58 preferably silicon nitride, also having protruding portions, is then deposited upon the first oxide. A chemical mechanical polish removes the mask protrusions to expose the first oxide layer. A second oxide layer 60 is then deposited. The first and second oxide layers are etched to form an opening 64 through to one of the conductive layers 54. A conductive plug 68 is then deposited to contact the one conductive layer 54. The first oxide layer is preferably deposited by High Density Plasma CVD or Plasma Enhanced CVD. An additional opening 66 through the second oxide layer may be formed and filled with conductive material. The conductive material is preferably tungsten, sputter deposited or deposited by CVD.

    Dual damascene technique
    5.
    发明专利
    Dual damascene technique 未知

    公开(公告)号：GB2340657B

    公开(公告)日：2000-07-05

    申请号：GB9812531

    申请日：1998-06-10

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： TSAI MENG-JIN

    IPC: H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768

    Abstract: The method comprises depositing, onto a substrate 50 which has conductive layers 54, a first oxide layer 56 which has protruding portions formed above the conductive layers 54. A mask layer 58 preferably silicon nitride, also having protruding portions, is then deposited upon the first oxide. A chemical mechanical polish removes the mask protrusions to expose the first oxide layer. A second oxide layer 60 is then deposited. The first and second oxide layers are etched to form an opening 64 through to one of the conductive layers 54. A conductive plug 68 is then deposited to contact the one conductive layer 54. The first oxide layer is preferably deposited by High Density Plasma CVD or Plasma Enhanced CVD. An additional opening 66 through the second oxide layer may be formed and filled with conductive material. The conductive material is preferably tungsten, sputter deposited or deposited by CVD.

    8.
    发明专利
    未知

    公开(公告)号：NL1009536C2

    公开(公告)日：2000-01-07

    申请号：NL1009536

    申请日：1998-07-01

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： TSAI MENG-JIN

    IPC: H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768

    Abstract: The method comprises depositing, onto a substrate 50 which has conductive layers 54, a first oxide layer 56 which has protruding portions formed above the conductive layers 54. A mask layer 58 preferably silicon nitride, also having protruding portions, is then deposited upon the first oxide. A chemical mechanical polish removes the mask protrusions to expose the first oxide layer. A second oxide layer 60 is then deposited. The first and second oxide layers are etched to form an opening 64 through to one of the conductive layers 54. A conductive plug 68 is then deposited to contact the one conductive layer 54. The first oxide layer is preferably deposited by High Density Plasma CVD or Plasma Enhanced CVD. An additional opening 66 through the second oxide layer may be formed and filled with conductive material. The conductive material is preferably tungsten, sputter deposited or deposited by CVD.

    Implanting nitride to produce gate oxide with different-thickness in hybrid and insertion ULSI
    10.
    发明专利
    Implanting nitride to produce gate oxide with different-thickness in hybrid and insertion ULSI 未知

    公开(公告)号：NL1006803C2

    公开(公告)日：1999-02-23

    申请号：NL1006803

    申请日：1997-08-20

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI ,  TSAI MENG-JIN

    IPC: H01L21/8239 ,  H01L27/105 ,  H01L21/316 ,  H01L21/8234

    Abstract: Production if an IC device requires the following steps to be performed - Provide semiconductor substrate with surface and that substrate has a 1st area, which will generate 1st MOS devices and a 2nd area which will generate several 2nd MOS devices; - Provide 1st dopant of 1st density on 1st area surface of substrate; - Provide 2nd dopant of 2nd density on 2nd area surface of substrate; - Oxidation substrate surface in single oxidation process, and generate oxide with 1st thickness on 1st area, and generate oxide with 2nd different thickness on 2nd area of substrate; - Generate 1st MOS device with 1st thickness oxide on 1st area, and generate 2nd MOS device with 2nd thickness oxide on 2nd area of substrate.

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