公开(公告)号：JPH11191615A

公开(公告)日：1999-07-13

申请号：JP7806298

申请日：1998-03-25

Applicant: UNITED MICROELECTRONICS CORP

Inventor： WU H J ,  SUN SHIH-WEI ,  CHIN SHIKI ,  YEW TRI-RUNG

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To form an integrated circuit device having respective arrays of a logic circuit and an embedded DRAM, while avoiding low yield. SOLUTION: A transfer FET 104 and a wiring line 106 are provided on an embedded DRAM circuit in the prestage of a process, while a logic FET 120 is provided on a logic circuit part. A gate electrode and source/drain regions of the logic 120 are made salicide in the initial stage, and a thick and planarized oxide layer is provided on the device. Next, a capacitor and a logic wiring are formed through the use of common etching, titanium nitride deposition and tungsten deposition steps. Then, in order to expose source/drain regions of the transfer FET 104, a contact via is formed. A titanium nitride layer is deposited on the device and in the contact via. Furthermore, after the selective removal of a capacitor dielectric layer provided on the device, a tungsten layer is pattern-formed to complete an upper capacitor electrode 158, a bit-line contact 160, and a logic circuit wiring 162.

公开(公告)号：JPH1126725A

公开(公告)日：1999-01-29

申请号：JP944898

申请日：1998-01-21

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To decrease the stress between an upper electrode and an interlayer insulating film and to prevent the cracking of the interlayer insulating film, by forming a titanium layer on the surface of the upper electrode of a capacitor formed on the surface of a dielectric film, and forming the interlayer insulating film on the entire surface on the lower structure so as to cover the titanium layer. SOLUTION: A lower electrode 59 is formed on the lower structure comprising rising a first interlayer insulating film 56 and the like, so as to be connected to a source/drain region 52 through a conducting layer 58 in a contact hole 57. Thereafter, a dielectric film 60 having the high dielectric constant such as barium titanate is formed on the surface of the lower electrode 59 and one exposed surface of one first interlayer insulating film 56. An upper electrode 61 of a capacitor is formed on the dielectric film 60. Thereafter, a titanium layer 62 is formed on the upper electrode 61. Then, a second interlayer insulating film 63 such as a borophosphosilicate glass layer or a phosphorus silicate glass layer is finally formed on the entire surface of the titanium layer 62 (the entire surface of the lower structured.

公开(公告)号：JPH10335456A

公开(公告)日：1998-12-18

申请号：JP14035397

申请日：1997-05-29

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YU SUIYO ,  RYU MOSHO ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit by a double Damascus process which can have a wide degree of process flexibility and can be easily applied to a mass production process. SOLUTION: An etch stop layer 54 is patterned to form an opening 72 corresponding to a pattern of connection of a 2level connection structure formed at a first level, on which an intermetallic dielectric layer 58 is provided, on which a photoresist mask 62 is provided. Openings 64 and 66 in the mask 62 partially expose the dielectric layer 58 as associated with a wiring pattern of the connection structure provided at a second level. The dielectric layer 58 is etched and advanced until an opening 68 is made in a part of a stop layer 54 of an interlayer dielectric layer 52 exposed to the opening 72. That is, the openings are defined through a single etching step for both of the second level wiring and first level connection. Next, a metal layer is formed on the structure and excess metal is removed therefrom to define a second level connection structure.

公开(公告)号：JPH11260917A

公开(公告)日：1999-09-24

申请号：JP27038298

申请日：1998-09-24

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RO KATETSU ,  SUN SHIH-WEI ,  KO MASUTAMI

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a barrier layer for increasing the capability of a barrier layer for increasing adhesive strength between a low k (Low-k) dielectric layer and a barrier layer, and for preventing the diffusion of barrier layer conductive materials, and a method for manufacturing the barrier layer. SOLUTION: This is a barrier layer and a method for forming the barrier layer includes the following process. At first, a semiconductor substrate having a conductive layer already formed on this is prepared. Next, an organic low (k) dielectric layer is deposited so that the conductive layer and the semiconductor substrate can be covered. Then, an opening for exposing the conductive layer is formed in the dielectric layer. Afterwards, a first barrier layer is deposited in the opening and the surrounding area. The first barrier layer can be a silicon-containing layer or a doped silicon (doped-Si) layer formed by a plasma enhanced CVD (PECVD) method, low pressure CVD (KPCVD) method, electronic beam overprizing method, or platter method. At last, a second barrier layer is formed by covering the first barrier layer. The second barrier layer can be a titanium/titanium nitride(Ti/TiN), tungsten nitride (WN) layer, tantalum(Ta) layer, or tantalum nitride(TaN) layer.

公开(公告)号：JPH11163523A

公开(公告)日：1999-06-18

申请号：JP30448097

申请日：1997-11-06

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI

IPC: H05K3/46 ,  H01L21/768 ,  H01L23/12 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming multilayer interconnection structure, which has a landless via hole for interlayer connection and uses air as dielectric between the wirings. SOLUTION: A carbon layer is deposited on the surface of an insulator and a groove corresponding to a wiring pattern is formed on the surface of the carbon layer. A metal is supplied into the groove and onto the surface of the carbon layer, and a first layer wiring 66 is obtained by the subsequent chemical mechanical polishing process. Carbon ashing or etch back process is performed on the carbon layer, and the surface of the carbon layer is made lower than the wiring plane. An oxide capping layer 70 is formed on the wiring plane and on the surface of the recessed carbon layer. The carbon layer is consumed and removed by the oxidation process through the capping layer 70, and an air gap 74 is formed. Then, a silicon nitride etching stop layer 72 is formed on the surface of the capping layer 70, and a dielectric layer 76 is formed on the capping layer 70. After filing a via hole with a metal plug 78, a second layer wiring 80 is formed.

公开(公告)号：JPH11145383A

公开(公告)日：1999-05-28

申请号：JP29840997

申请日：1997-10-30

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG

IPC: H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method with which an integrated circuit device which can suppress the plasma damages of a gate electrode in an FET logic circuit, and at the same time, the polycrystalline silicon loss of the gate electrode can be made reduced. SOLUTION: An integrated circuit device is formed in such a way that protective layers 129 having shapes in match with that of a substrate are formed on a plurality of transfer FETs 104 and a logic FET 120, so that the film thicknesses of the layer 129 on a gate electrode 124 and source/drain regions 118 of the logic FET 120 become nearly equal to each other. Then the source/ drain regions 118 of one transfer FET 104 is exposed by forming a contact opening by removing a part of the protective layer 129, and a lower capacitor electrode 130 is formed so that the electrode 130 comes into contact with the source/drain regions 118. After the formation of the capacitor electrode 130, a charge storage capacitor with respect to the transfer FET is formed, by forming a capacitor dielectric layer 132 and an upper capacitor electrode 134 on the lower capacitor electrode 130. Thereafter, the protective layer 129 is removed from at least a part of its logic circuit region.

公开(公告)号：JPH11121616A

公开(公告)日：1999-04-30

申请号：JP27781497

申请日：1997-10-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To fill an unfilled via region, facilitate a gap filling process and prevent a void formation, by a method wherein a metal layer is deposited on wiring lines and in a gap between the wiring lines. SOLUTION: A dielectric material 40 is a silicon oxide layer or a borophosphosilicate glass layer, and a contact opening or via 44 is formed on a metal, polysilicon or an active region in a lower portion in a substrate 42. A first metal layer 46 uniformly fills the via 44 and the filled rear face is an aluminum or tungsten layer deposited so as to be flatted substantially to form a photoresist mask, and a first metal layer 46 is exposed and removed to make patterns of a wiring line. Next, an opening in the via is buried by deposition of a second metal layer to finish as a metal sidewalk spacer structure. Then, a remaining portion is extended to form a second sidewall structure to thereby prevent a void wherein contaminant accumulates from keing farmed.

公开(公告)号：JPH10335662A

公开(公告)日：1998-12-18

申请号：JP21623597

申请日：1997-08-11

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN KENTEI ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To prevent current leakage, increase the sizes of a contact window and lessen a metal silicide in contact resistance and surface resistance, by taking advantage of a slope in a process where ions are diffused into source/drain regions of MOS components. SOLUTION: Self-aligned silicides each provided with an impurity diffusion region 29 are formed below source/drain regions 27 adjacent to isolation regions 24. This forming method comprises a step where ions are implanted, taking advantage of an angle of inclination. By this method, the source/drain regions 27 are increased in junction depth, and a metal silicide provided to the edge of the isolation region 24 is restrained from excessively approaching a source/ drain junction. The isolation regions 24 are subjected to over etching, whereby the surfaces of the isolation regions 24 are exposed. A metal silicide layer 31 is formed on the surfaces of the source/drain regions respectively, and a region used for the formation of a wide border contact window 34 is enlarged in area.

公开(公告)号：US6362101B2

公开(公告)日：2002-03-26

申请号：US97660597

申请日：1997-11-24

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YANG MING-SHENG ,  WU JUAN-YUAN ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/304 ,  C09K3/14 ,  H01L21/321 ,  H01L21/302

CPC classification number: H01L21/3212 ,  C09K3/1463

Abstract: A method for chemical mechanical polishing a component includes providing an oxide layer and forming at least one via through the oxide layer. A tungsten layer is formed within the via and over the oxide layer. A first chemical mechanical polishing step is carried out on a polishing pad using a first slurry having an oxidizing component and having a pH of approximately 2 to approximately 4 to remove the tungsten layer from over the oxide layer. A second chemical mechanical polishing step is carried out on the polishing pad using a second slurry having a pH of approximately 2 to approximately 4 to polish scratches out of the oxide layer.

Abstract translation: 用于化学机械抛光组分的方法包括提供氧化物层并通过氧化物层形成至少一个通孔。 在通孔内和氧化物层上形成钨层。 在抛光垫上使用具有氧化成分的第一浆料并且具有约2至约4的pH进行第一化学机械抛光步骤以从氧化物层上方除去钨层。 使用pH为约2〜约4的第二浆料在抛光垫上进行第二化学机械抛光步骤以抛光出氧化物层的划痕。

公开(公告)号：JP2003179140A

公开(公告)日：2003-06-27

申请号：JP2002358268

申请日：2002-12-10

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RYU MOSHO ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L21/3065 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit by a double-damascene process which exhibits a wide process flexibility and can be easily adapted in mass-production process. SOLUTION: After an etch stop layer 54 is patterned for forming an opening 72 corresponding to a pattern in a connection which is formed on the first level of a two-level connection structure, an intermetallic dielectric layer 58 is provided on it and a photoresist mask 62 is provided on it. Openings 64 and 66 of the mask 62 correspond to the wiring pattern provided on the second level of the connection structure and a dielectric layer 58 is partially exposed from them. The dielectric layer 58 is etched and the etching is advanced in such a way that an opening 68 is produced in the exposed part of the stop layer 54 from the opening 72 of the interlayer dielectric layer 52. In other words, openings for both of the wiring on the second level and the connection on the first level are demarcated by a single etching process. Further, the opening 72 of the stop layer is tapered with its upper diameter being larger than its lower diameter. COPYRIGHT: (C)2003,JPO