公开(公告)号：EP2669935A3

公开(公告)日：2017-12-27

申请号：EP12191602.7

申请日：2012-11-07

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang, Tseng ,  Dyi-Chung, Hu

IPC: H01L21/48 ,  H01L23/498

Abstract: A packaging substrate (100) including following elements is provided. The insulation supporting layer (120) is disposed on a first surface (112) of the multilayered interconnect board (110) and has an opening region (R10). A portion of the first surface (112) is exposed at the opening region (R10). The interposer (130) is disposed on the first surface (112) at the opening region (R10). A third surface (130A) of the interposer (130) faces the first surface (112) of the multilayered interconnect board (110). A stress releasing gap (136) is between an outer-sidewall of the interposer (130) and an inner-sidewall of the opening region (R10). The compliant layer (170) is disposed between the third surface (130A) and the first surface (112). The interposer (130) has through holes (132) and conductive posts (134) disposed in the through holes (132). The conductive posts (134) penetrate the compliant layer (170) and electrically connect with the multilayered interconnect board (110). The redistribution layer (140) is disposed on a fourth surface (130B) of the interposer (130) and is electrically connected with the conductive posts (134).

Abstract translation: 提供了包括以下元件的封装基板（100）。 绝缘支撑层（120）设置在多层互连板（110）的第一表面（112）上并具有开口区域（R10）。 第一表面（112）的一部分在开口区域（R10）处暴露。 中介层（130）在开口区域（R10）处设置在第一表面（112）上。 中介层（130）的第三表面（130A）面向多层互连板（110）的第一表面（112）。 应力释放间隙（136）位于插入件（130）的外侧壁与开口区域（R10）的内侧壁之间。 柔性层（170）设置在第三表面（130A）和第一表面（112）之间。 中介层（130）具有设置在通孔（132）中的通孔（132）和导电柱（134）。 导电柱（134）穿过柔性层（170）并与多层互连板（110）电连接。 再分布层140设置于中介层130的第四表面130B上并与导电柱134电性连接。

公开(公告)号：EP2669935B1

公开(公告)日：2020-04-22

申请号：EP12191602.7

申请日：2012-11-07

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang, Tseng ,  Dyi-Chung, Hu

IPC: H01L21/48 ,  H01L23/498

公开(公告)号：EP2669935A2

公开(公告)日：2013-12-04

申请号：EP12191602.7

申请日：2012-11-07

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang, Tseng ,  Dyi-Chung, Hu

IPC: H01L21/48 ,  H01L23/498

Abstract: A packaging substrate (100) including following elements is provided. The insulation supporting layer (120) is disposed on a first surface (112) of the multilayered interconnect board (110) and has an opening region (R10). A portion of the first surface (112) is exposed at the opening region (R10). The interposer (130) is disposed on the first surface (112) at the opening region (R10). A third surface (130A) of the interposer (130) faces the first surface (112) of the multilayered interconnect board (110). A stress releasing gap (136) is between an outer-sidewall of the interposer (130) and an inner-sidewall of the opening region (R10). The compliant layer (170) is disposed between the third surface (130A) and the first surface (112). The interposer (130) has through holes (132) and conductive posts (134) disposed in the through holes (132). The conductive posts (134) penetrate the compliant layer (170) and electrically connect with the multilayered interconnect board (110). The redistribution layer (140) is disposed on a fourth surface (130B) of the interposer (130) and is electrically connected with the conductive posts (134).

Abstract translation: 提供包括以下元件的封装基板（100）。 绝缘支撑层（120）设置在多层互连板（110）的第一表面（112）上并具有开口区域（R10）。 第一表面（112）的一部分在开口区域（R10）处露出。 插入器（130）在开口区域（R10）处设置在第一表面（112）上。 内插器（130）的第三表面（130A）面向多层互连板（110）的第一表面（112）。 应力释放间隙（136）位于插入件（130）的外侧壁和开口区域（R10）的内侧壁之间。 柔性层（170）设置在第三表面（130A）和第一表面（112）之间。 插入器（130）具有设置在通孔（132）中的通孔（132）和导电柱（134）。 导电柱（134）穿透顺应层（170）并与多层互连板（110）电连接。 再分配层（140）设置在插入件（130）的第四表面（130B）上并与导电柱（134）电连接。