公开(公告)号：US20190035792A1

公开(公告)日：2019-01-31

申请号：US15876216

申请日：2018-01-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tsuo-Wen Lu ,  Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/10823 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28211 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66621

Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.

公开(公告)号：US10056388B2

公开(公告)日：2018-08-21

申请号：US15465622

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Yung-Ming Wang ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L29/423 ,  H01L27/108 ,  H01L21/265 ,  H01L29/10 ,  H01L29/49 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/10876 ,  H01L21/76237 ,  H01L27/10823 ,  H01L29/1037 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/4236 ,  H01L29/495 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; performing a first ion implantation process to form a first doped region having a first conductive type in the substrate adjacent to the trench; forming a gate electrode in the trench; and performing a second ion implantation process to form a second doped region having a second conductive type in the substrate above the gate electrode.

公开(公告)号：US20180190660A1

公开(公告)日：2018-07-05

申请号：US15465622

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Yung-Ming Wang ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L27/108 ,  H01L21/265 ,  H01L29/423 ,  H01L29/10 ,  H01L29/49 ,  H01L21/762

CPC classification number: H01L27/10876 ,  H01L21/26513 ,  H01L21/76237 ,  H01L27/10823 ,  H01L29/1037 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/4236 ,  H01L29/495 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; performing a first ion implantation process to form a first doped region having a first conductive type in the substrate adjacent to the trench; forming a gate electrode in the trench; and performing a second ion implantation process to form a second doped region having a second conductive type in the substrate above the gate electrode.

公开(公告)号：US20200235101A1

公开(公告)日：2020-07-23

申请号：US16841702

申请日：2020-04-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Cheng Tsai ,  Chih-Chi Cheng ,  Chia-Wei Wu ,  Ger-Pin Lin

IPC: H01L27/108

Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.

公开(公告)号：US10217750B1

公开(公告)日：2019-02-26

申请号：US15712133

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Kuan-Chun Lin ,  Chi-Mao Hsu ,  Shu-Yen Chan ,  Shih-Fang Tzou ,  Tsuo-Wen Lu ,  Tien-Chen Chan ,  Feng-Yi Chang ,  Shih-Kuei Yen ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/28

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

公开(公告)号：US20180197868A1

公开(公告)日：2018-07-12

申请号：US15866482

申请日：2018-01-10

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Yung-Ming Wang ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L21/76 ,  H01L21/02 ,  H01L21/3115

CPC classification number: H01L27/10891 ,  H01L21/02164 ,  H01L21/31155 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/76237

Abstract: A semiconductor device and a manufacturing method thereof include providing a substrate including an active region of a conductivity type and an isolation structure, in which the isolation structure surrounds the active region; forming a word line trench on the substrate, the word line trench intersecting the active region; and forming two doped regions in the active region at two sides of the word line trench respectively, in which each doped region and a bottom surface of the word line trench are located in a same level, and each doped region includes dopants of the conductivity type or an intrinsic semiconductor dopants.

公开(公告)号：US20180190771A1

公开(公告)日：2018-07-05

申请号：US15854769

申请日：2017-12-27

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L29/08 ,  H01L27/108 ,  H01L29/167 ,  H01L23/535 ,  H01L21/265 ,  H01L21/223

CPC classification number: H01L29/0847 ,  H01L21/2236 ,  H01L21/26513 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/1082 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/167

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate, at least one active area is defined on the substrate, a buried word line is disposed in the substrate, a source/drain region disposed beside the buried word line, a diffusion barrier region, disposed at the top of the source/drain region, the diffusion barrier region comprises a plurality of doping atoms selected from the group consisting of carbon atoms, nitrogen atoms, germanium atoms, oxygen atoms, helium atoms and xenon atoms, a dielectric layer disposed on the substrate, and a contact structure disposed in the dielectric layer, and electrically connected to the source/drain region.

公开(公告)号：US20150104914A1

公开(公告)日：2015-04-16

申请号：US14551922

申请日：2014-11-24

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Ching-Nan Hwang ,  Chi-Heng Lin ,  Chun-Yao Yang ,  Ger-Pin Lin ,  Ching-I Li

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/3215 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L21/26593 ,  H01L21/02532 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/0629 ,  H01L28/20

Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is cryo-implanted with at least two of multiple species including a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.

Abstract translation: 提供半导体工艺，包括以下步骤。 在基板上形成多晶硅层。 多晶硅层在-40℃至-120℃的温度范围内用至少两种多种物质进行低温注入，包括锗物质，碳物质和p型或n型物质。不对称 对多晶硅层进行双面加热处理，其中用于正面加热的功率与用于背面加热的功率不同。

公开(公告)号：US10658365B2

公开(公告)日：2020-05-19

申请号：US16052636

申请日：2018-08-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Cheng Tsai ,  Chih-Chi Cheng ,  Chia-Wei Wu ,  Ger-Pin Lin

IPC: H01L27/108

Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.

公开(公告)号：US20190164977A1

公开(公告)日：2019-05-30

申请号：US16226648

申请日：2018-12-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Kuan-Chun Lin ,  Chi-Mao Hsu ,  Shu-Yen Chan ,  Shih-Fang Tzou ,  Tsuo-Wen Lu ,  Tien-Chen Chan ,  Feng-Yi Chang ,  Shih-Kuei Yen ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/28

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.