公开(公告)号：WO1995024276A1

公开(公告)日：1995-09-14

申请号：PCT/US1995002749

申请日：1995-03-07

Applicant: VISTATECH CORPORATION

Inventor： VISTATECH CORPORATION ,  RAINWATER, Jewel, G. ,  BENSON, Paul ,  BELKO, William, R. ,  DEFFEYES, Robert, J. ,  CARLSON, Arne, B.

IPC: B05D01/36

CPC classification number: H01L21/4857 ,  H01G4/308 ,  H01L21/4867 ,  H01L21/67236 ,  H05K3/4664

Abstract: The invention is a new method of making an electrode embedded green sheet. Electrodes (1), surround dielectric (3), and dielectric overcoat (5) are printed onto a green sheet. After each step, calendaring is performed.

Abstract translation: 本发明是一种制作电极嵌入式生片的新方法。 电极（1），环绕电介质（3）和电介质外涂层（5）印刷在生片上。 在每个步骤之后，执行日历。

公开(公告)号：WO1993019857A1

公开(公告)日：1993-10-14

申请号：PCT/US1993002990

申请日：1993-03-30

Applicant: VISTATECH CORPORATION

Inventor： VISTATECH CORPORATION ,  RAINWATER, Jewel, G.

IPC: B05D05/12

CPC classification number: H01L21/67236 ,  H01G4/308 ,  H01L21/4857 ,  H01L21/4867 ,  H05K3/4664

Abstract: A method for making a substrate for use in a multilayered integrated circuit or multichip module which includes coating a conductive material (14) on a surface of a support sheet (10) to form a conductive circuit (12) and then drying the sheet. Next, a coating of a layer of dielectric layer (18) is placed on the support surface in the areas where the conductive material is not cast. After which the coated sheet is densified to form a densified conductive circuit embedded dielectric layer. A second coating of a dielectric (28) is placed over the first densified conductive circuit embedded dielectric layer such that the second layer is characterized by vias (30) therein which are in register with at least a portion of the conductive circuit (12). The vias in the second dielectric layer are filled to form electrically conductive vias and then densified to form the substrate (44).

Abstract translation: 一种制造用于多层集成电路或多芯片模块的衬底的方法，包括在支撑片（10）的表面上涂覆导电材料（14）以形成导电电路（12），然后干燥片材。 接下来，将电介质层（18）的涂层放置在导电材料不被铸造的区域中的支撑表面上。 之后，将被覆层片致密化，形成致密化的导电电路嵌入介质层。 电介质（28）的第二涂层被放置在第一致密化的导电电路嵌入介电层上，使得第二层的特征在于其中与导电电路（12）的至少一部分对准的通孔（30）。 填充第二电介质层中的通孔以形成导电通孔，然后致密化以形成衬底（44）。