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    2.
    发明专利
    未知

    公开(公告)号：DE69606834D1

    公开(公告)日：2000-04-06

    申请号：DE69606834

    申请日：1996-11-28

    Applicant: XEROX CORP

    Inventor： HAWKINS WILLIAM G ,  REZANKA IVAN ,  MARKHAM ROGER G ,  IMS DALE R ,  DRAKE DONALD J

    IPC: B41J2/21 ,  B41J2/01 ,  B41J2/05 ,  B41J2/15 ,  B41J2/155 ,  B41J2/525 ,  B41J3/54

    Abstract: An ink jet printer (8) is configured in a hybrid architecture wherein a full width printbar (10) is combined with a partial width color scanning assembly (21) to provide the capability of selectively printing in black only or, alternately, of producing color prints by operating the color scan assembly (21) exclusively. The cost of the hybrid system, when compared to a full width color system using four full width printbars, is greatly reduced. Throughput time is reduced by providing the control circuitry (42) for distinguishing between black only and color operation and selectively controlling the printer mode of operation. The hybrid architecture is particularly useful in a LAN system since it provides a mechanism for balancing the relative color versus black page decomposition speed limitations. Also, the hybrid architecture enables a relatively simple implementation of a checkerboarding technique to suppress banding in output prints.

    3.
    发明专利
    未知

    公开(公告)号：DE69033135D1

    公开(公告)日：1999-07-08

    申请号：DE69033135

    申请日：1990-11-22

    Applicant: XEROX CORP

    Inventor： DRAKE DONALD J ,  HAWKINS WILLIAM G ,  CAMPANELLI MICHAEL R ,  TELLIER THOMAS A

    IPC: B41J2/05 ,  B41J2/135 ,  B41J2/16 ,  H01L21/301 ,  H01L21/306 ,  H01L21/308 ,  H01L21/768 ,  H01L21/78

    Abstract: At least one through opening of predetermined location and dimensions is fabricated in a (100) silicon wafer (30) by orientation dependent etching method after completion of integrated circuits (33) on the wafer, the opening extending through the wafer between a circuit surface (31) of the wafer and an opposite parallel base surface (32) of the wafer and having a predetermined location relative to the integrated circuit on the circuit surface of the wafer. The method includes the steps of fabricating the integrated circuit on the circuit surface of the wafer; applying an etch resistant layer (34) of plasma silicon nitride on the circuit and base surfaces of the wafer; patterning the etch resistant plasma silicon nitride layer on the circuit surface to define an upper etch opening (35) having a location and dimensions which define the predetermined location and dimensions of the through opening; and patterning the plasma silicon nitride layer on the base surface to produce a lower etch opening (36) aligned with the upper etch opening within a predetermined tolerance. The wafer is then anisotropically etched to produce a first recess (37) corresponding to the upper etch opening in the circuit surface and a second recess (38) corresponding to the lower etch opening in the base surface, each of the first and second recesses being bounded by (111) plane side walls. The anisotropic etching of the second recess intersects the first recess to form the through opening bounded by (111) plane side walls and has its predetermined dimensions and location defined by the patterning of the upper etch opening.

    INK SUPPLY IDENTIFICATION SYSTEM
    5.
    发明专利
    INK SUPPLY IDENTIFICATION SYSTEM 未知

    公开(公告)号：CA2164536A1

    公开(公告)日：1996-07-04

    申请号：CA2164536

    申请日：1995-12-06

    Applicant: XEROX CORP

    Inventor： HAWKINS WILLIAM G

    IPC: B41J2/175 ,  B41J29/42

    Abstract: A printer having an ink supply identification system includes an ink supply, an ink supply identification corresponding to the ink supply, a memory to store the ink supply identification and printer data, a control device for comparing the ink supply identification to the printer data stored in the memory and for controlling the operation of the printer in response to the ink supply identification, and a print element connected to the ink supply and the control device. The printer has increased reliability that enables a high quality printed image to be produced consistently.

    6.
    发明专利
    未知

    公开(公告)号：DE69331363T2

    公开(公告)日：2002-06-20

    申请号：DE69331363

    申请日：1993-09-22

    Applicant: XEROX CORP

    Inventor： HAWKINS WILLIAM G ,  WATROBSKI THOMAS E ,  VANDEROEK SOPHIE ,  BURKE CATHIE J ,  TELLIER THOMAS A

    IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

    Abstract: An electrostatic discharge protection (ESD) device for a connector associated with an integrated circuit chip, particularly one associated with a thermal ink-jet printhead. A MOS field effect device (60) extends along at least one edge of the connector (32) on the chip. A bipolar transistor (66-70), parasitic to the field effect device (60), conducts current from the connector (32) to ground (52) in response to a voltage between the connector (32) and ground (52) in excess of a predetermined threshold. A zone (90) of a predetermined electrical resistance is operatively disposed between the bipolar transistor (66-70) and ground (52). The zone (90) may substantially encircle (Fig 4) the bonding pad (32) of the connector to evenly distribute local incidences of high voltage. The invention enables integrated circuits to pass ESD requirements of office products, which is 15kV by Human Body Model testing.

    8.
    发明专利
    未知

    公开(公告)号：DE69331363D1

    公开(公告)日：2002-01-31

    申请号：DE69331363

    申请日：1993-09-22

    Applicant: XEROX CORP

    Inventor： HAWKINS WILLIAM G ,  WATROBSKI THOMAS E ,  VANDEROEK SOPHIE ,  BURKE CATHIE J ,  TELLIER THOMAS A

    IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

    Abstract: An electrostatic discharge protection (ESD) device for a connector associated with an integrated circuit chip, particularly one associated with a thermal ink-jet printhead. A MOS field effect device (60) extends along at least one edge of the connector (32) on the chip. A bipolar transistor (66-70), parasitic to the field effect device (60), conducts current from the connector (32) to ground (52) in response to a voltage between the connector (32) and ground (52) in excess of a predetermined threshold. A zone (90) of a predetermined electrical resistance is operatively disposed between the bipolar transistor (66-70) and ground (52). The zone (90) may substantially encircle (Fig 4) the bonding pad (32) of the connector to evenly distribute local incidences of high voltage. The invention enables integrated circuits to pass ESD requirements of office products, which is 15kV by Human Body Model testing.

    9.
    发明专利
    未知

    公开(公告)号：ES2142549T3

    公开(公告)日：2000-04-16

    申请号：ES96308602

    申请日：1996-11-28

    Applicant: XEROX CORP

    Inventor： HAWKINS WILLIAM G ,  REZANKA IVAN ,  MARKHAM ROGER G ,  IMS DALE R ,  DRAKE DONALD J

    IPC: B41J2/21 ,  B41J2/01 ,  B41J2/05 ,  B41J2/15 ,  B41J2/155 ,  B41J2/525 ,  B41J3/54

    Abstract: An ink jet printer (8) is configured in a hybrid architecture wherein a full width printbar (10) is combined with a partial width color scanning assembly (21) to provide the capability of selectively printing in black only or, alternately, of producing color prints by operating the color scan assembly (21) exclusively. The cost of the hybrid system, when compared to a full width color system using four full width printbars, is greatly reduced. Throughput time is reduced by providing the control circuitry (42) for distinguishing between black only and color operation and selectively controlling the printer mode of operation. The hybrid architecture is particularly useful in a LAN system since it provides a mechanism for balancing the relative color versus black page decomposition speed limitations. Also, the hybrid architecture enables a relatively simple implementation of a checkerboarding technique to suppress banding in output prints.

    10.
    发明专利
    未知

    公开(公告)号：DE69319021T2

    公开(公告)日：1998-12-10

    申请号：DE69319021

    申请日：1993-05-04

    Applicant: XEROX CORP

    Inventor： HAWKINS WILLIAM G

    IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

    Abstract: An electrostatic discharge (ESD) protection device (18) for protecting a high voltage operating circuit having a high voltage input terminal (12) is disclosed. The ESD protection circuit has a substrate (20), a first diffusion region (68) formed in the substrate connected to the high voltage input terminal, a second diffusion region (70) formed in the substrate connected to ground, a field oxide layer (66) over the substrate having a thickened region (66a) extending into the substrate between the first and second diffusion regions, and a drift region (78) formed in the substrate and located between the first diffusion region and the thickened field oxide layer. These regions are so arranged to move the point of avalanche breakdown away from the first diffusion/field oxide interface, so that the avalanche breakdown voltage is lower than that of the protected circuit while simultaneously preventing avalanche included bipolar feedback in the protection device.

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