公开(公告)号：US6361331B2

公开(公告)日：2002-03-26

申请号：US92360001

申请日：2001-08-06

Applicant: XEROX CORP

Inventor： FORK DAVID KIRTLAND ,  HO JACKSON ,  LAU RACHEL KING-HA ,  LU JENGPING

IPC: B81B3/00 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  H01L23/498 ,  H01R4/48 ,  H01R12/00 ,  H01R12/57 ,  H05K3/40 ,  H01R9/09

CPC classification number: G01R1/06716 ,  B81B2203/0118 ,  B81C1/00484 ,  B81C2201/0136 ,  B81C2203/058 ,  G01R1/06727 ,  G01R1/07342 ,  G01R3/00 ,  H01L23/49811 ,  H01L2924/0002 ,  H01R4/48 ,  H01R12/57 ,  H05K3/4092 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/4914 ,  H01L2924/00

Abstract: Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad or metal via, and also to further anchor the spring metal finger to the substrate.

Abstract translation: 通过使用单个掩模通过形成弹簧金属和释放材料层来将含有接触垫或金属通孔的弹性结构光刻制造到衬底上的有效方法。 具体地说，使用光致抗蚀剂掩模或电镀金属图案或使用剥离处理技术，释放材料垫与弹簧金属手指自对准。 然后使用释放掩模释放弹簧金属指，同时保持将弹簧金属指的锚固部分固定到基底的释放材料的一部分。 当释放材料是导电的（例如钛）时，该释放材料部分直接位于接触垫或金属通孔上方，并且用作在完成的弹簧结构中的弹簧金属指的导管。 当释放材料不导电时，形成金属带以将弹簧金属指连接到接触垫或金属通孔，并且还将弹簧金属指状物进一步锚定到基底。

公开(公告)号：DE69118151D1

公开(公告)日：1996-04-25

申请号：DE69118151

申请日：1991-12-23

Applicant: XEROX CORP

Inventor： MIKKELSEN JAMES C ,  MEULI WILLIAM ,  BRUCE RICHARD ,  HO JACKSON

IPC: G09F9/00 ,  G09F9/35 ,  G09F9/40 ,  H01R4/02 ,  H01R4/04 ,  H01R12/52 ,  H05K1/11 ,  H05K1/14 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36

Abstract: A method for electrically connecting planar element substrates (12) to form an array (10) by forming conductive bridges (16) between metal pads (14) located on the surface of array elements (12). The conductive bridges (16) are formed to be nearly coplanar with the planar elements (12) and are made to connect the end faces (14b) of pads (14) which are fused to the planar substrate (12). Metal wire (16a), solder (16b-c), a conductive polymer (16d), or a suspension of conductive particles in paste (16e) are used to form the bridges. The bridges (16) have a low profile, occupy a very small area and reduce the need for highly accurate alignment of adjacent substrates (12) within the tiled array (10) before electrical connections are formed. These low profile bridges (16) are especially advantageous tn that they allow a protective plastics or similar cover sheet, or a liquid crystal laminate, to be surface mounted on the adjacent array (10) without causing detrimental surface blemishes or ridges. The small area of the bridges (16) greatly reduces the non-transmitting area of the visual display. The bridges (16), being substantially narrower than the pads (14) which they connect, are more likely to connect the intended pads (14) and less likely to "short" pads (14) which are not in accurate alignment.

公开(公告)号：DE60029907D1

公开(公告)日：2006-09-21

申请号：DE60029907

申请日：2000-11-17

Applicant: XEROX CORP

Inventor： HO JACKSON ,  FULKS RONALD T

IPC: H01L21/336 ,  H01L29/786

Abstract: A top gate, self-aligned polysilicon (poly-Si) thin film transistor (TFT) is formed using a single laser anneal to crystallize the active silicon and to activate the source-drain region. The poly-Si TFT includes a substrate, dummy gate, a barrier oxide layer, a polysilicon pattern having a source region and a drain region, a gate oxide, and a gate.

公开(公告)号：CA2110967A1

公开(公告)日：1994-06-29

申请号：CA2110967

申请日：1993-12-08

Applicant: XEROX CORP

Inventor： CHUANG TZU-CHIN ,  HO JACKSON

IPC: G02F1/13 ,  G02F1/133 ,  G02F1/1333 ,  G02F1/1339 ,  G02F1/1362

Abstract: A flat panel liquid crystal display, and method for forming the display, wherein spacers are lithographically patterned and etched on the cover sheet of the display, and the cover sheet is assembled on an active matrix substrate with the spacers directed toward the active matrix substrate. A liquid crystal material is provided in the gap between the cover sheet and active matrix substrate. The active matrix substrate may have pixels thereon each having a plurality of components, with the spacers being aligned with the same element of each of a plurality of the pixels.

公开(公告)号：EP0745885A3

公开(公告)日：1998-05-06

申请号：EP96303898

申请日：1996-05-30

Applicant: XEROX CORP

Inventor： YAO WILLIAM ,  FULKS RONALD T ,  HO JACKSON

IPC: G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/786 ,  G02F1/1335

CPC classification number: G02F1/136227 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/1214

Abstract: The invention provides an integrated dark matrix for an active matrix liquid crystal display. A plurality of pixel electrodes (38,72) overlap (710) at least one of a plurality of gate lines (34) and a plurality of data lines (32). A perimeter of the pixel electrodes overlaps the gate lines and/or data lines by twice the distance (718) that the pixel electrode is above the gate and data lines, respectively to obtain a viewing angle of over 60 degrees.

公开(公告)号：DE60029907T2

公开(公告)日：2007-01-25

申请号：DE60029907

申请日：2000-11-17

Applicant: XEROX CORP

Inventor： HO JACKSON ,  FULKS RONALD T

IPC: H01L21/336 ,  H01L29/786

Abstract: A top gate, self-aligned polysilicon (poly-Si) thin film transistor (TFT) is formed using a single laser anneal to crystallize the active silicon and to activate the source-drain region. The poly-Si TFT includes a substrate, dummy gate, a barrier oxide layer, a polysilicon pattern having a source region and a drain region, a gate oxide, and a gate.

公开(公告)号：DE69118151T2

公开(公告)日：1996-10-10

申请号：DE69118151

申请日：1991-12-23

Applicant: XEROX CORP

Inventor： MIKKELSEN JAMES C ,  MEULI WILLIAM ,  BRUCE RICHARD ,  HO JACKSON

IPC: G09F9/00 ,  G09F9/35 ,  G09F9/40 ,  H01R4/02 ,  H01R4/04 ,  H01R12/52 ,  H05K1/11 ,  H05K1/14 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36

Abstract: A method for electrically connecting planar element substrates (12) to form an array (10) by forming conductive bridges (16) between metal pads (14) located on the surface of array elements (12). The conductive bridges (16) are formed to be nearly coplanar with the planar elements (12) and are made to connect the end faces (14b) of pads (14) which are fused to the planar substrate (12). Metal wire (16a), solder (16b-c), a conductive polymer (16d), or a suspension of conductive particles in paste (16e) are used to form the bridges. The bridges (16) have a low profile, occupy a very small area and reduce the need for highly accurate alignment of adjacent substrates (12) within the tiled array (10) before electrical connections are formed. These low profile bridges (16) are especially advantageous tn that they allow a protective plastics or similar cover sheet, or a liquid crystal laminate, to be surface mounted on the adjacent array (10) without causing detrimental surface blemishes or ridges. The small area of the bridges (16) greatly reduces the non-transmitting area of the visual display. The bridges (16), being substantially narrower than the pads (14) which they connect, are more likely to connect the intended pads (14) and less likely to "short" pads (14) which are not in accurate alignment.