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    USO DE UNA RANURA EN U COMO UNA ALTERNATIVA AL USO DE UNA RANURA EN V PARA PROTEGER SILICIO CONTRA DANO INDUCIDO POR CORTE.
    4.
    发明专利
    USO DE UNA RANURA EN U COMO UNA ALTERNATIVA AL USO DE UNA RANURA EN V PARA PROTEGER SILICIO CONTRA DANO INDUCIDO POR CORTE. 未知

    公开(公告)号：MXPA02011802A

    公开(公告)日：2004-09-03

    申请号：MXPA02011802

    申请日：2002-11-28

    Applicant: XEROX CORP

    Inventor： SALATINO NICHOLAS J

    IPC: B28D5/02 ,  H01L21/301 ,  H01L21/3065 ,  G01R31/26

    Abstract: La descripcion de la presente invencion se relaciona con la modificacion de la metodologia para cortar o separar matrices de microcircuitos integrados a un perfil de ranura en U de un perfil de ranura en V modificando el segundo paso de grabado para que sea un grabado en seco en lugar de un grabado en humedo que da como resultado ahorros de costos directos eliminando un paso de proceso mas caro, asi como la necesidad de separar la capa de sustancia fotoendurecible desarrollada. Ademas, el desplazamiento a un perfil de ranura en U logra ahorros de costos indirectos adicionales y aun mayores resultantes del incremento del rendimiento del proceso, mejor rendimiento, y reduccion de los defectos de la capa de metal.

    METHOD FOR DICING SEMICONDUCTOR WAFER AND MANUFACTURING METHOD FOR DIE
    5.
    发明专利
    METHOD FOR DICING SEMICONDUCTOR WAFER AND MANUFACTURING METHOD FOR DIE 审中-公开

    公开(公告)号：JP2003188117A

    公开(公告)日：2003-07-04

    申请号：JP2002343713

    申请日：2002-11-27

    Applicant: XEROX CORP

    Inventor： PERREGAUX ALAIN E ,  HOSIER PAUL A ,  JEDLICKA JOSEF E ,  SALATINO NICHOLAS J ,  TANDON JAGDISH C

    IPC: B28D5/02 ,  H01L21/301 ,  H01L21/3065

    Abstract: PROBLEM TO BE SOLVED: To provide a method which can cut an edge part of a die very nearby an active element on the die, never damages the active element, and dices the die from a semiconductor wafer. SOLUTION: The present disclosure that by modifying chip die dicing methodology to a U-groove profile 300 from a V-groove profile by modifying the second etch step to be a dry etch instead of a wet etch results in a direct cost savings by eliminating a more expensive process step, as well as the need for stripping the developed photoresist layer. Furthermore, using of a U-groove profile 300 accomplishes additional indirect and greater cost savings resulting from increased process throughput, improved yield, and reduced metal layer defects. COPYRIGHT: (C)2003,JPO

    Method for dicing semiconductor wafer, chip diced from semiconductor wafer, and array of chips diced from semiconductor wafer
    6.
    发明专利
    Method for dicing semiconductor wafer, chip diced from semiconductor wafer, and array of chips diced from semiconductor wafer 有权
    半导体晶片切割半导体晶片的方法，半导体晶片的晶圆阵列

    公开(公告)号：JP2011135075A

    公开(公告)日：2011-07-07

    申请号：JP2010281107

    申请日：2010-12-17

    Applicant: Xerox Corp ,  ゼロックス コーポレイションXerox Corporation

    Inventor： HOSIER PAUL A ,  SALATINO NICHOLAS J

    IPC: H01L21/301 ,  B23K26/38 ,  B23K26/40

    CPC classification number: H01L23/544 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To implement high-accuracy and low-damage dicing suitable for dicing chips for array. SOLUTION: For dicing a semiconductor wafer 100, a rear surface of the wafer 100 is first diced, to form a reference slot 106 and the rear surface of the wafer is diced; while it is aligned with respect to the slot 106, to form a rear surface slot 112. The desired location for a chip edge is determined, with the reference slot 106 as a basis; edges 130, 138 of a laser beam 126, as radiant energy, are aligned with respect to the desired location for the chip edge, such that they range to the rear surface slot 112; and the beam 126 is supplied inside the wafer 100. Then, since the crystalline structure of the wafer 100 varies along a supply path and generates reformed regions 128, 136, the wafer 100 is divided with the line of the reformed region 128 as a boundary. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：实现适用于阵列切割芯片的高精度和低损伤切割。 解决方案：为了切割半导体晶片100，首先对晶片100的后表面进行切割，以形成参考槽106，并且切割晶片的后表面; 同时它相对于槽106对准以形成后表面槽112.用参考槽106作为基准确定用于芯片边缘的期望位置; 作为辐射能量的激光束126的边缘130,138相对于芯片边缘的期望位置对齐，使得它们到后表面槽112; 并且光束126被供给到晶片100的内部。然后，由于晶片100的晶体结构沿着供给路径而变化，并且产生重整区域128,136，所以将晶片100与重整区域128的线分开作为边界 。 版权所有（C）2011，JPO＆INPIT

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