公开(公告)号：WO2003025804A3

公开(公告)日：2003-03-27

申请号：PCT/US2002/028531

申请日：2002-09-06

Applicant: XILINX, INC.

Inventor： HART, Michael, J. ,  YOUNG, Steven, P. ,  GITLIN, Daniel ,  SHEN, Hua ,  TRIMBERGER, Stephen, M.

IPC: G06F17/50

Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables Positive well biasing only forthe transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

公开(公告)号：WO2009055129A1

公开(公告)日：2009-04-30

申请号：PCT/US2008/073529

申请日：2008-08-18

Applicant: XILINX, INC.

Inventor： LUO, Yuhao ,  WU, Shuxian ,  WU, Xin X. ,  AHN, Jae-Gyung ,  NAYAK, Deepak Kumar ,  GITLIN, Daniel

IPC: H01L27/02

CPC classification number: H01L27/0251

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Abstract translation: 公开了一种保护形成在集成电路的管芯上的晶体管的方法。 该方法包括在晶片上形成晶体管的有源区; 在有源区上形成晶体管的栅极; 将初级接触耦合到晶体管的栅极; 在所述晶体管的栅极和保护元件之间耦合可编程元件; 以及通过可编程元件将保护元件与晶体管的栅极去耦合。 还公开了用于保护形成在集成电路的管芯上的晶体管的电路。

公开(公告)号：WO2003025804A2

公开(公告)日：2003-03-27

申请号：PCT/US2002/028531

申请日：2002-09-06

Applicant: XILINX, INC.

Inventor： HART, Michael, J. ,  YOUNG, Steven, P. ,  GITLIN, Daniel ,  SHEN, Hua ,  TRIMBERGER, Stephen, M.

IPC: G06F17/50

CPC classification number: H03K19/17792 ,  G06F17/5054 ,  H01L27/0928 ,  H01L27/11807

Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables Positive well biasing only forthe transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

Abstract translation: 用于选择性地将阱偏压施加到PLD的那些需要或期望的偏置的那些部分的结构和方法，例如在用户设计中的关键路径上的晶体管施加正的阱偏置。 用于集成电路的衬底包括多个阱，每个阱可以以相同或不同的阱偏置电压独立地且可编程地偏置。 在一个实施例中，FPGA实现软件自动确定关键路径并产生配置比特流，其使得仅对参与关键路径的晶体管施加正阱偏置，或仅对包含那些晶体管的可编程逻辑元件（例如，CLB或查找表）进行极性偏置。 在另一个实施例中，选择性地施加负阱偏置以减少泄漏电流。

公开(公告)号：EP1428155A2

公开(公告)日：2004-06-16

申请号：EP02798937.5

申请日：2002-09-06

Applicant: Xilinx, Inc.

Inventor： HART, Michael, J. ,  YOUNG, Steven, P. ,  GITLIN, Daniel ,  SHEN, Hua ,  TRIMBERGER, Stephen, M.

IPC: G06F17/50

CPC classification number: H03K19/17792 ,  G06F17/5054 ,  H01L27/0928 ,  H01L27/11807

Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables Positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

公开(公告)号：EP1428155B1

公开(公告)日：2006-11-29

申请号：EP02798937.5

申请日：2002-09-06

Applicant: Xilinx, Inc.

Inventor： HART, Michael, J. ,  YOUNG, Steven, P. ,  GITLIN, Daniel ,  SHEN, Hua ,  TRIMBERGER, Stephen, M.

IPC: G06F17/50 ,  H03K19/00

CPC classification number: H03K19/17792 ,  G06F17/5054 ,  H01L27/0928 ,  H01L27/11807

Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables Positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.