公开(公告)号：KR20200139714A

公开(公告)日：2020-12-14

申请号：KR20207030487

申请日：2019-04-01

Applicant: XILINX INC

Inventor： ANSARI AHMAD R ,  BURTON FELIX ,  CHEN MING DONG

IPC: G06F11/36 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/267 ,  G06F11/273

Abstract: 회로장치는 SoC(system-on-chip)(102) 상에배치되고스트리밍디버그패킷을수신하고저장하도록구성된하나이상의입력버퍼(312, 314,…, 316)를포함한다. 하나이상의응답버퍼(328, 330,…, 332)도또한 SoC 상에배치된다. 트랜잭션제어회로(318)는 SoC 상에배치되고하나이상의입력버퍼내의각 디버그패킷을처리하도록구성된다. 처리는디버그패킷내의동작코드를디코딩하고, 디버그패킷내의어드레스로부터 SoC 상의다수의서브시스템의서브시스템에서스토리지회로에액세스하기위하여다수의인터페이스회로의인터페이스회로를결정하는것을포함한다. 처리는동작코드에따라스토리지회로에액세스하는요청을인터페이스회로를통하여발행하고, 인터페이스회로로부터수신된응답및 데이터를하나이상의응답버퍼에저장하는것을더 포함한다.

公开(公告)号：CA2434031A1

公开(公告)日：2002-07-18

申请号：CA2434031

申请日：2001-12-10

Applicant: XILINX INC

Inventor： VASHI MEHUL R ,  ANSARI AHMAD R ,  YOUNG STEVEN P ,  SASTRY PRASAD L ,  YIN ROBERT ,  DOUGLASS STEPHEN M

IPC: G06F12/06 ,  G06F13/16 ,  G06F15/78 ,  H03K19/173 ,  G06F12/00

Abstract: A data processing system having a user configurable memory controller, local block RAMs, global block RAMs and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the global block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. The number of wait states of the local block RAM is also user selectable. An algorithm that can optimize the addres s depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

公开(公告)号：DE60332098D1

公开(公告)日：2010-05-27

申请号：DE60332098

申请日：2003-02-21

Applicant: XILINX INC

Inventor： ANSARI AHMAD R ,  DOUGLASS STEPHEN M

IPC: H01L21/82 ,  H03K19/177 ,  H03K19/173

公开(公告)号：CA2434031C

公开(公告)日：2007-06-19

申请号：CA2434031

申请日：2001-12-10

Applicant: XILINX INC

Inventor： ANSARI AHMAD R ,  VASHI MEHUL R ,  YOUNG STEVEN P ,  SASTRY PRASAD L ,  YIN ROBERT ,  DOUGLASS STEPHEN M

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F15/78 ,  H03K19/173

Abstract: A data processing system having a user configurable memory controller, local block RAMs, global block RAMs and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the global block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. The number of wait states of the local block RAM is also user selectable. An algorithm that can optimize the addres s depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

公开(公告)号：CA2476175C

公开(公告)日：2009-05-26

申请号：CA2476175

申请日：2003-02-21

Applicant: XILINX INC

Inventor： ANSARI AHMAD R ,  DOUGLASS STEPHEN M

IPC: H01L21/82 ,  H03K19/177 ,  H03K19/173

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnectin g tiles and may further include interconnecting logic. The interconnecting til es provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interconnecting logic, when included, provides logic circuitry that conditio ns data transfers between the fixed logic circuit and the programmable logic fabric. The invention is directed towards the various needs and requirements of the layout and floor planning of a device having both fixed logic circuit ry and programmable logic circuitry. The various designs are geared towards man y goals including allowing fail-safe operation, facilitating the ease of interface between fixed logic circuitry and programmable logic fabric, among other issues.

公开(公告)号：CA2476175A1

公开(公告)日：2003-09-04

申请号：CA2476175

申请日：2003-02-21

Applicant: XILINX INC

Inventor： ANSARI AHMAD R ,  DOUGLASS STEPHEN M

IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnectin g tiles and may further include interconnecting logic. The interconnecting til es provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interconnecting logic, when included, provides logic circuitry that conditio ns data transfers between the fixed logic circuit and the programmable logic fabric. The invention is directed towards the various needs and requirements of the layout and floor planning of a device having both fixed logic circuit ry and programmable logic circuitry. The various designs are geared towards man y goals including allowing fail-safe operation, facilitating the ease of interface between fixed logic circuitry and programmable logic fabric, among other issues.

公开(公告)号：WO02056180A3

公开(公告)日：2003-12-04

申请号：PCT/US0147743

申请日：2001-12-10

Applicant: XILINX INC

Inventor： ANSARI AHMAD R ,  DOUGLASS STEPHEN M ,  VASHI MEHUL R ,  YOUNG STEVEN P ,  SASTRY PRASAD L ,  YIN ROBERT

IPC: G06F12/06 ,  G06F13/16 ,  G06F15/78 ,  H03K19/173

CPC classification number: G06F13/1689 ,  G06F15/7867

Abstract: A data processing system having a user configurable memory controller, local block RAMs, global block RAMs and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the global block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. The number of wait states of the local block RAM is also user selectable. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

Abstract translation: 具有用户可配置存储器控制器，本地块RAM，全局块RAM和处理器核的数据处理系统可以被配置在单个现场可编程门阵列（FPGA）中。 全局块RAM的地址深度和等待状态数可以由用户选择，并且可以在配置FPGA之前设置，也可以使用处理器核心的指令进行编程。 本地块RAM的等待状态数也是用户可选择的。 还公开了可以优化地址深度和等待状态数以达到性能水平的算法。 本发明可以应用于具有单独的指令和数据侧的设计。