公开(公告)号：KR20180053314A

公开(公告)日：2018-05-21

申请号：KR20187008097

申请日：2016-09-09

Applicant: XILINX INC

Inventor： GAIDE BRIAN C ,  YOUNG STEVEN P ,  KAVIANI ALIREZA S

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17728 ,  H03K19/1737 ,  H03K19/17776

Abstract: 예에서, 프로그래머블집적회로(IC)를위한구성가능논리소자는, 제1 입력및 제1 출력, 그리고제1 입력과제1 출력사이에연결된제1 합논리(312-0) 및제1 자리올림논리(310-0)를포함하는제1 룩업테이블(LUT)(302-0); 제2 입력및 제2 출력, 그리고제2 입력과제2 출력사이에연결된제2 합논리(312-1)를포함하는제2 LUT(302-1); 및제1 및제2 LUT에각각연결된제1 및제2 캐스케이드멀티플렉서(322-0, 322-1)를포함하고, 제2 캐스케이드멀티플렉서의입력이제1 LUT에서의제1 자리올림논리의출력에연결된다.

公开(公告)号：CA2411650C

公开(公告)日：2012-11-27

申请号：CA2411650

申请日：2001-04-06

Applicant: XILINX INC

Inventor： CARBERRY RICHARD A ,  YOUNG STEVEN P ,  BAUER TREVOR J

IPC: H03K19/177 ,  H03K19/173

Abstract: A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and second LUT.

公开(公告)号：DE60131078T2

公开(公告)日：2008-08-07

申请号：DE60131078

申请日：2001-04-06

Applicant: XILINX INC

Inventor： CARBERRY RICHARD A ,  YOUNG STEVEN P ,  BAUER TREVOR J

IPC: H03K19/00 ,  H03K19/173 ,  H03K19/177

Abstract: A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and second LUT.

公开(公告)号：CA2548327A1

公开(公告)日：2005-07-21

申请号：CA2548327

申请日：2004-12-21

Applicant: XILINX INC

Inventor： NEW BERNARD J ,  WONG JENNIFER ,  YOUNG STEVEN P ,  CHING ALVIN Y ,  SIMKINS JAMES M

IPC: G06F15/78 ,  G06F15/80 ,  H03K19/177

Abstract: Described is an integrated circuit (IC) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP sli ce includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conve ys processed results. Each slice additionally includes a feedback port connecte d to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

公开(公告)号：CA2458060A1

公开(公告)日：2003-04-10

申请号：CA2458060

申请日：2002-09-23

Applicant: XILINX INC

Inventor： YOUNG STEVEN P ,  DOUGLASS STEPHEN M ,  VASHI MEHUL R ,  HERRON NIGEL G ,  SOWARDS JANE W

IPC: H01L21/82 ,  G06F15/78 ,  H03K19/173

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnectin g tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric.

公开(公告)号：CA2704707C

公开(公告)日：2015-10-06

申请号：CA2704707

申请日：2008-10-21

Applicant: XILINX INC

Inventor： KARP JAMES ,  YOUNG STEVEN P ,  NEW BERNARD J ,  NANCE SCOTT S ,  CROTTY PATRICK J

IPC: G06F17/50 ,  H01L21/58 ,  H01L23/48 ,  H01L25/065 ,  H03K19/177

Abstract: Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the hybrid integrated circuit device (400) using at least in part a first minimum dimension lithography. A second die (300) is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die (300) has the second minimum dimension lithography as a smallest lithography used for the forming of the second die (300). The first die (200) and the second die (300) are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device (400).

公开(公告)号：CA2676132C

公开(公告)日：2012-01-03

申请号：CA2676132

申请日：2001-04-06

Applicant: XILINX INC

Inventor： CARBERRY RICHARD A ,  YOUNG STEVEN P ,  BAUER TREVOR J

IPC: H03K19/177 ,  H03K19/173

Abstract: A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and second LUT.

公开(公告)号：CA2434031C

公开(公告)日：2007-06-19

申请号：CA2434031

申请日：2001-12-10

Applicant: XILINX INC

Inventor： ANSARI AHMAD R ,  VASHI MEHUL R ,  YOUNG STEVEN P ,  SASTRY PRASAD L ,  YIN ROBERT ,  DOUGLASS STEPHEN M

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F15/78 ,  H03K19/173

Abstract: A data processing system having a user configurable memory controller, local block RAMs, global block RAMs and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the global block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. The number of wait states of the local block RAM is also user selectable. An algorithm that can optimize the addres s depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

公开(公告)号：CA2424706A1

公开(公告)日：2002-04-11

申请号：CA2424706

申请日：2001-10-05

Applicant: XILINX INC

Inventor： GOETTING F ERICH ,  LOGUE JOHN D ,  PERCEY ANDREW K ,  YOUNG STEVEN P ,  CHING ALVIN Y

IPC: G06F1/10 ,  H03L7/081 ,  H04L7/00 ,  G06F1/04

Abstract: After a delay lock loop (300) synchronizes a reference clock signal with a skewed clock signal (REF-CLK), a digital phase shifter (350) can be used to shift the skewed clock signal (S-CLK) by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line (310) in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal.

公开(公告)号：CA2409214A1

公开(公告)日：2001-11-29

申请号：CA2409214

申请日：2001-05-17

Applicant: XILINX INC

Inventor： YOUNG STEVEN P ,  PANG RAYMOND C

IPC: G11C11/413 ,  G11C7/10 ,  G11C8/16 ,  G11C11/41 ,  H03K19/173 ,  H03K19/177 ,  H03K19/00

Abstract: A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of write modes for accessing the memory cell array. In one embodiment, the write modes include a write with write-back mode, a write without write-back mode, and a read then write mode. The control logic selects the write mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the write mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) write modes. The widths of the first and second ports can also be independently configured.