公开(公告)号：WO2010087892A3

公开(公告)日：2011-03-10

申请号：PCT/US2009065589

申请日：2009-11-23

Applicant: XILINX INC

Inventor： CONSTANTIN CICAL I ,  CULLEN EDWARD

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C5/147

Abstract: A circuit for reducing power consumption in input ports of an integrated circuit (102) is disclosed. The circuit comprises a plurality of receiver circuits (112, 114, 116, 118) of the integrated circuit (102) for receiving input signals coupled to the integrated circuit (102); and a bias current generator (122) coupled to the plurality of receiver circuits (112, 114, 116, 118), the bias current generator (122) providing a bias voltage for each receiver circuit of the plurality of receiver circuits (112, 114, 116, 118) to mirror the current in the bias current generator (122) in each of the receiver circuits (112, 114, 116, 118). A method of reducing power consumption in input ports of an integrated circuit (102) is also disclosed.

Abstract translation: 公开了一种降低集成电路（102）输入端口功耗的电路。 该电路包括用于接收耦合到集成电路（102）的输入信号的集成电路（102）的多个接收器电路（112,114,116,118）。 以及耦合到所述多个接收器电路（112,114,116,118）的偏置电流发生器（122），所述偏置电流发生器（122）为所述多个接收器电路（112,114）中的每个接收器电路提供偏置电压 ，116,118,118,118,116,118），用于镜像每个接收器电路（112,114,116,118）中的偏置电流发生器（122）中的电流。 还公开了一种降低集成电路（102）输入端口功耗的方法。

公开(公告)号：WO2014051894A3

公开(公告)日：2014-09-18

申请号：PCT/US2013055993

申请日：2013-08-21

Applicant: XILINX INC

Inventor： ERDMANN CHRISTOPHE ,  CULLEN EDWARD ,  LOWNEY DONNACHA

IPC: H01L23/498 ,  H01L23/552

CPC classification number: H01L23/49827 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0655 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer (203) has first vias (211). First interconnects (205) and second interconnects (206) respectively are coupled on opposite surfaces of the interposer (203). A first portion of the first interconnects (205) and a second portion of the first interconnects (205) are spaced apart from one another defining an isolation region (220) between them. A substrate (204) has second vias (212). Third interconnects (207) and the second interconnects (206) are respectively coupled on opposite surfaces of the package substrate (204). A first portion of the first vias (211) and a first portion of the second vias (212) are both in the isolation region (220) and are coupled to one another with a first portion of the second interconnects (206).

Abstract translation: 公开了一种装置的实施例。 对于该装置的该实施例，插入器（203）具有第一通孔（211）。 第一互连（205）和第二互连（206）分别耦合在插入器（203）的相对表面上。 第一互连（205）的第一部分和第一互连（205）的第二部分彼此间隔开，在它们之间限定隔离区域（220）。 衬底（204）具有第二通孔（212）。 第三互连（207）和第二互连（206）分别耦合在封装衬底（204）的相对表面上。 第一通孔（211）的第一部分和第二通孔（212）的第一部分都在隔离区域（220）中并且用第二互连件（206）的第一部分彼此耦合。