公开(公告)号：JPH04242825A

公开(公告)日：1992-08-31

申请号：JP13557691

申请日：1991-05-10

Applicant: XILINX INC

Inventor： HANGUUCHIENGU SHII ,  UIRIAMU ESU KAATAA ,  CHIYAARUZU AARU ERIKUSON ,  EDOMONDO WAI CHIENGU

IPC: G06F7/50 ,  G06F7/506 ,  G06F7/57

Abstract: PURPOSE: To provide exclusive hardware in a logic block in order to quickly execute a carry function by the smallest number of components. CONSTITUTION: Two single bits A, B to be added are impressed to two input terminals of an XOR gate 51. When the bits A, B are equal, a low level output from the gate 51 turns on a pass transistor(TR) T1 and turns off a pass TR T2 to allow the passage of a signal to a carry-out terminal Cout . When the bits A, B are different from each other, an output from the gate 51 is in a high level, so that the TR T2 is turned on and the TR T1 is turned off. Consequently a signal from a carry-in terminal Cin can be passed to the carry-out terminal Cout .