公开(公告)号：CA2424706A1

公开(公告)日：2002-04-11

申请号：CA2424706

申请日：2001-10-05

Applicant: XILINX INC

Inventor： GOETTING F ERICH ,  LOGUE JOHN D ,  PERCEY ANDREW K ,  YOUNG STEVEN P ,  CHING ALVIN Y

IPC: G06F1/10 ,  H03L7/081 ,  H04L7/00 ,  G06F1/04

Abstract: After a delay lock loop (300) synchronizes a reference clock signal with a skewed clock signal (REF-CLK), a digital phase shifter (350) can be used to shift the skewed clock signal (S-CLK) by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line (310) in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal.

公开(公告)号：CA2424702A1

公开(公告)日：2002-04-11

申请号：CA2424702

申请日：2001-10-05

Applicant: XILINX INC

Inventor： GOETTING F ERICH ,  PERCEY ANDREW K ,  LOGUE JOHN D

IPC: G06F1/06 ,  G06F1/10 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00 ,  H03L7/06 ,  G06F1/04

Abstract: A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchonized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a dela y lock loop and a digital frequency synthesizer. The delay lock loop and a digital frequency synthesizer. The output clock signal lags the synchrozing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matchin g the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal .

公开(公告)号：CA2424706C

公开(公告)日：2010-12-14

申请号：CA2424706

申请日：2001-10-05

Applicant: XILINX INC

Inventor： YOUNG STEVEN P ,  LOGUE JOHN D ,  PERCEY ANDREW K ,  GOETTING F ERICH ,  CHING ALVIN Y

IPC: H03L7/081 ,  G06F1/04 ,  G06F1/10 ,  H04L7/00

Abstract: After a delay lock loop (300) synchronizes a reference clock signal with a skewed clock signal (REF-CLK), a digital phase shifter (350) can be used to shift the skewed clock signal (S-CLK) by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line (310) in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal.

公开(公告)号：CA2424702C

公开(公告)日：2009-09-08

申请号：CA2424702

申请日：2001-10-05

Applicant: XILINX INC

Inventor： LOGUE JOHN D ,  PERCEY ANDREW K ,  GOETTING F ERICH

IPC: H03L7/06 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00

Abstract: A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchonized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a dela y lock loop and a digital frequency synthesizer. The delay lock loop and a digital frequency synthesizer. The output clock signal lags the synchrozing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matchin g the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal .

公开(公告)号：WO0229975A3

公开(公告)日：2003-03-27

申请号：PCT/US0131450

申请日：2001-10-05

Applicant: XILINX INC

Inventor： YOUNG STEVEN P ,  LOGUE JOHN D ,  PERCEY ANDREW K ,  GOETTING F ERICH ,  CHING ALVIN Y

IPC: G06F1/10 ,  H03L7/081 ,  H04L7/00 ,  G06F1/04

CPC classification number: G06F1/10 ,  H03L7/0814

Abstract: After a delay lock loop (300) synchronizes a reference clock signal with a skewed clock signal (REF-CLK), a digital phase shifter (350) can be used to shift the skewed clock signal (S-CLK) by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line (310) in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal.

Abstract translation: 在延迟锁定环路（300）使参考时钟信号与偏斜时钟信号（REF-CLK）同步之后，数字移相器（350）可用于将偏斜的时钟信号（S-CLK）移位少量与 相对于参考时钟信号。 在延迟锁定环路的主路径中的延迟线（310）的抽头/微调设置可被发送到数字移相器，从而向数字移相器通知参考时钟信号的周期。 作为响应，数字移相器提供相位控制信号，其将参考时钟信号或偏斜时钟信号引入延迟。 相位控制信号与参考时钟信号的周期的预定分数成比例。

公开(公告)号：WO0229974A3

公开(公告)日：2003-03-27

申请号：PCT/US0131251

申请日：2001-10-05

Applicant: XILINX INC

Inventor： LOGUE JOHN D ,  PERCEY ANDREW K ,  GOETTING F ERICH

IPC: G06F1/06 ,  G06F1/10 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00 ,  H03L7/06 ,  G06F1/04

CPC classification number: H03L7/07 ,  G06F1/10 ,  H03L7/0814

Abstract: A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchonized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop and a digital frequency synthesizer. The output clock signal lags the synchrozing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.

Abstract translation: 提供数字时钟管理器。 数字时钟管理器产生一个输出时钟信号，使得偏斜的时钟信号与参考时钟信号同步。 此外，数字时钟管理器产生在同步期间与输出时钟信号同步的频率调整时钟信号。 数字时钟管理器包括延迟锁定环和数字频率合成器。 延时锁定环和数字频率合成器。 输出时钟信号通过DLL输出延迟滞后于同步时钟信号。 类似地，频率调整的时钟信号通过DFS输出延迟滞后于同步时钟信号。 通过将DLL输出延迟与DFS输出延迟相匹配，数字时钟管理器将输出时钟信号和频率调整后的时钟信号同步。