公开(公告)号：CA2548327A1

公开(公告)日：2005-07-21

申请号：CA2548327

申请日：2004-12-21

Applicant: XILINX INC

Inventor： NEW BERNARD J ,  WONG JENNIFER ,  YOUNG STEVEN P ,  CHING ALVIN Y ,  SIMKINS JAMES M

IPC: G06F15/78 ,  G06F15/80 ,  H03K19/177

Abstract: Described is an integrated circuit (IC) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP sli ce includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conve ys processed results. Each slice additionally includes a feedback port connecte d to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

公开(公告)号：CA2548327C

公开(公告)日：2015-10-20

申请号：CA2548327

申请日：2004-12-21

Applicant: XILINX INC

Inventor： SIMKINS JAMES M ,  YOUNG STEVEN P ,  WONG JENNIFER ,  NEW BERNARD J ,  CHING ALVIN Y

IPC: G06F15/78 ,  G06F15/80 ,  H03K19/177

Abstract: Described is an integrated circuit (IC) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

公开(公告)号：WO2005066832A3

公开(公告)日：2006-01-19

申请号：PCT/US2004043113

申请日：2004-12-21

Applicant: XILINX INC

Inventor： SIMKINS JAMES M ,  YOUNG STEVEN P ,  WONG JENNIFER ,  NEW BERNARD J ,  CHING ALVIN Y

IPC: G06F15/78 ,  G06F15/80 ,  H03K19/177

CPC classification number: H03K19/17736 ,  G06F15/7867 ,  H03K19/17732 ,  H03K19/17796

Abstract: Described is an integrated circuit (IC) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

Abstract translation: 描述的是具有可以级联的DSP片段的集成电路（IC），以创建不同大小和复杂性的DSP电路。 每个DSP片包括多个操作数输入端口和片输出端口，所有这些端口都可编程地连接到通用路由和逻辑资源。 操作数端口接收处理的操作数，切片输出端口传送处理结果。 每个切片还包括连接到相应切片输出端口的反馈端口，以支持在该实施例中的累积功能，以及连接到上游切片的输出端口以支持级联的级联输入端口。