公开(公告)号：US08923463B1

公开(公告)日：2014-12-30

申请号：US14013283

申请日：2013-08-29

Applicant: Xilinx, Inc.

Inventor： Michael O. Jenkins ,  Cheng-Hsiang Hsieh

IPC: H04L7/02 ,  H04L25/02

CPC classification number: H04L7/0334 ,  H04L25/069

Abstract: In an apparatus, a receiver includes a clock data recovery module to provide a dense distribution of waveform edges across an adjustment range, and an eye scan circuit to obtain samples at a first sample position and a second sample position to provide an error count for a sample count for the samples. An eye scan module, coupled to the receiver, is configured to: scan for the samples at the first sample position of a first type for each of a plurality of sample positions of a second type to obtain an error count for a sample count for each of the plurality of sample positions; locate a threshold BER from the scan; determine an amount and a direction of a sample offset at the threshold BER from a reference location; and adjust either the first sample position or the second sample position responsive to the amount and the direction.

Abstract translation: 在一种装置中，接收机包括时钟数据恢复模块，用于在调整范围内提供波形边缘的密集分布，以及眼睛扫描电路，以获得在第一采样位置和第二采样位置处的采样，以提供误差计数 样品的样品数量。 耦合到接收器的眼睛扫描模块被配置为：针对第二类型的多个样本位置中的每一个扫描第一类型的第一样本位置处的样本，以获得每个样本计数的错误计数 的多个样本位置; 从扫描中定位阈值BER; 从参考位置确定在阈值BER处的样本偏移的量和方向; 并且响应于量和方向来调整第一样品位置或第二样品位置。

公开(公告)号：US11038768B1

公开(公告)日：2021-06-15

申请号：US15267002

申请日：2016-09-15

Applicant: Xilinx, Inc.

Inventor： Ivan O. Madrigal ,  Michael O. Jenkins ,  Hong S. Ahn ,  Murtuza Z. Cutleriwala ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans ,  Geoffrey Zhang ,  Hongtao Zhang

IPC: H04L25/03 ,  H04L12/24 ,  G06F30/331

Abstract: A method relates generally to comparison of a communications system modelled with a behavioral model and implemented with a circuit realization. In this method, operation of the communications system is simulated with the behavioral model on a computing device to obtain a first pulse response. The simulating includes first equalizing first data with a first equalizer of the behavioral model to obtain the first pulse response. The circuit realization is operated to obtain a second pulse response. The operating includes: second equalizing second data corresponding to the first data with a second equalizer of the circuit realization to obtain the second pulse response. The second pulse response from the circuit realization is loaded to memory of the computing device. The first pulse is loaded to the memory of the computing device. The first pulse response and the second pulse response are compared with one another by the computing device.

公开(公告)号：US09264211B1

公开(公告)日：2016-02-16

申请号：US14549197

申请日：2014-11-20

Applicant: Xilinx, Inc.

Inventor： Michael O. Jenkins

IPC: H04L7/00 ,  H03L7/091 ,  H03L7/081

CPC classification number: H04L7/0025 ,  H03F1/3241 ,  H03F1/3282 ,  H03L7/081 ,  H03L7/091 ,  H04L7/0087

Abstract: In an exemplary system, a first sampling circuit is coupled to a clock module to receive values therefrom. A second sampling circuit is coupled to the clock module to receive the values therefrom. The first sampling circuit includes a first converter, a first phase interpolator, and a first sampler. The first converter is coupled to replace the values with first replacement values for input to the first phase interpolator. The second sampling circuit includes a second converter, a second phase interpolator, and a second sampler. The second converter is coupled to replace the values with second replacement values for input to the second phase interpolator.

Abstract translation: 在示例性系统中，第一采样电路耦合到时钟模块以从其接收值。 第二采样电路耦合到时钟模块以从其接收值。 第一采样电路包括第一转换器，第一相位内插器和第一采样器。 第一转换器被耦合以用第一替换值替换值以输入到第一相位内插器。 第二采样电路包括第二转换器，第二相位内插器和第二采样器。 第二转换器被耦合以用第二替换值替换以输入到第二相位内插器的值。

公开(公告)号：US09065601B1

公开(公告)日：2015-06-23

申请号：US13842604

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Michael O. Jenkins ,  Cheng-Hsiang Hsieh ,  Christopher J. Borrelli

IPC: H04L7/04 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0337 ,  H03L7/0812 ,  H03L7/093 ,  H04L7/0025 ,  H04L7/033

Abstract: A receiver in an integrated circuit device is described. The circuit comprises a receiver having a clock and data recovery circuit coupled to receive data signals modulated with a transmitter clock signal; and a clock generator coupled to receive an output of the clock and data recovery circuit, the clock generator providing a modulated reference clock to the receiver, based upon a reference clock signal which is independent of the transmitter clock signal; wherein the modulated reference clock provided to the receiver is synchronized with the transmitter clock signal. A method of receiving data in an integrated circuit is also described.

Abstract translation: 描述了集成电路器件中的接收器。 该电路包括具有时钟和数据恢复电路的接收器，该时钟和数据恢复电路被耦合以接收用发射机时钟信号调制的数据信号; 以及时钟发生器，其耦合以接收所述时钟和数据恢复电路的输出，所述时钟发生器基于独立于所述发射机时钟信号的参考时钟信号向所述接收机提供调制参考时钟; 其中提供给接收机的调制参考时钟与发射机时钟信号同步。 还描述了在集成电路中接收数据的方法。