公开(公告)号：US11824534B2

公开(公告)日：2023-11-21

申请号：US17455195

申请日：2021-11-16

Applicant: XILINX, INC.

Inventor： Nakul Narang ,  Siok Wei Lim ,  Luhui Chen ,  Yipeng Wang ,  Kee Hian Tan

IPC: H04L25/02 ,  H03K19/17736 ,  G06F13/10 ,  H03K19/17788 ,  H04J3/04

CPC classification number: H03K19/17744 ,  G06F13/102 ,  H03K19/17788 ,  H04J3/047 ,  H04L25/0272

Abstract: A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.

公开(公告)号：US09853642B1

公开(公告)日：2017-12-26

申请号：US15234667

申请日：2016-08-11

Applicant: Xilinx, Inc.

Inventor： Kee Hian Tan ,  Kok Lim Chan ,  Siok Wei Lim

IPC: H03K3/00 ,  H03K19/0185 ,  H03H17/06 ,  H03M9/00 ,  H04L25/03

CPC classification number: H03K19/018521 ,  H03H17/06 ,  H03M9/00 ,  H04L25/03343

Abstract: An example output driver includes a plurality of output circuits coupled in parallel between a first voltage supply node and a second voltage supply node. Each of the plurality of output circuits includes a differential input that is coupled to receive a logic signal of a plurality of logic signals and a differential output that is coupled to a common output node. The output driver further includes voltage regulator(s), coupled to the voltage supply node(s), and a current compensation circuit. The current compensation circuit includes a switch coupled in series with a current source, where the switch and the current source are coupled between the first voltage supply node and the second voltage supply node. An event detector is coupled to the switch to supply an enable signal and to control state of the enable signal based on presence of a pattern in the plurality of logic signals.

公开(公告)号：US09742597B1

公开(公告)日：2017-08-22

申请号：US15084351

申请日：2016-03-29

Applicant: Xilinx, Inc.

Inventor： Kun-Yung Chang ,  Siok Wei Lim ,  Kee Hian Tan

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L25/4902 ,  H04L2025/03363 ,  H04L2025/03375 ,  H04L2025/03484 ,  H04L2025/03764

Abstract: An apparatus includes a decision feedback equalizer configured to receive a parallel signal generated based on a first clock. The decision feedback equalizer includes a first equalization block configured to receive a first symbol of a first set of parallel symbols provided by the parallel signal during a first clock cycle of the first clock. A decision feedback equalization is performed by the first equalization block to the first symbol to provide a first decision to a second equalization block. The second equalization block is configured to receive a second symbol of the first set of parallel symbols and perform a decision feedback equalization to the second symbol using the first decision received from the first equalization block to provide a second decision during the first clock cycle.

公开(公告)号：US10419067B1

公开(公告)日：2019-09-17

申请号：US16107712

申请日：2018-08-21

Applicant: Xilinx, Inc.

Inventor： Chin Yang Koay ,  Hongyuan Zhao ,  Siok Wei Lim ,  Kee Hian Tan

IPC: H04B3/20 ,  H04L7/027 ,  H04B3/493 ,  H04L25/02

Abstract: Apparatus and associated methods relate to a programmable resistor having a resistance iteratively programmed by a calibration control loop. In an illustrative example, the calibration control loop may alternately sample the programmable resistance and a reference resistance by producing a corresponding voltage drop across the resistors. The voltage drops may, for example, be induced by the same constant current source. The calibration control loop may compare the voltage drops with a comparator, for example. In some examples, the comparator may provide a count direction signal to a logic block, generating a calibration code. The calibration code may, for example, be applied to the programmable resistor, such that the resistance of the programmable resistor iteratively approaches the resistance of the reference resistor. Various programmable resistors within a calibration control loop may, for example, substantially improve termination impedances of high-speed transmission lines and may mitigate random resistive mismatch variations.

公开(公告)号：US10033412B2

公开(公告)日：2018-07-24

申请号：US15837791

申请日：2017-12-11

Applicant: Xilinx, Inc.

Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC: H03K17/687 ,  H04B1/04 ,  H03M9/00 ,  H02M3/158

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

公开(公告)号：US20180102797A1

公开(公告)日：2018-04-12

申请号：US15837791

申请日：2017-12-11

Applicant: Xilinx, Inc.

Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04B1/04 ,  H03M9/00 ,  H02M3/158 ,  H03K17/687

CPC classification number: H04B1/04 ,  H02M3/158 ,  H03K17/163 ,  H03K17/6872 ,  H03K19/0175 ,  H03M9/00

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

公开(公告)号：US09887710B1

公开(公告)日：2018-02-06

申请号：US15227853

申请日：2016-08-03

Applicant: Xilinx, Inc.

Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04B1/04 ,  H03K17/687 ,  H03M9/00 ,  H02M3/158

CPC classification number: H04B1/04 ,  H02M3/158 ,  H03K17/163 ,  H03K17/6872 ,  H03K19/0175 ,  H03M9/00

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

公开(公告)号：US11855652B2

公开(公告)日：2023-12-26

申请号：US17643349

申请日：2021-12-08

Applicant: XILINX, INC.

Inventor： Hao-Wei Hung ,  Tan Kee Hian ,  Siok Wei Lim ,  Hongtao Zhang

IPC: H03M1/10 ,  H03M9/00 ,  H03M1/66

CPC classification number: H03M1/1023 ,  H03M1/1047 ,  H03M9/00 ,  H03M1/66

Abstract: A multiplexer (MUX) calibration system includes main MUX circuitry, first replica MUX circuitry, digital-to-analog (DAC) circuitry, detection circuitry, and control circuitry. The main MUX circuitry receives clock signals and outputs a first data signal based on the clock signals. The first replica MUX circuitry receives the clock signals and outputs a second data signal based on the clock signals. The DAC circuitry generates an offset voltage. The detection circuitry receives the second data signal and the offset voltage and generates a first error signal based on one or more of the second data signal and the offset voltage. The control circuitry receives the first error signal and generates a first control signal indicating an adjustment to the clock signals.

公开(公告)号：US20180041232A1

公开(公告)日：2018-02-08

申请号：US15227853

申请日：2016-08-03

Applicant: Xilinx, Inc.

Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04B1/04 ,  H03M9/00 ,  H02M3/158 ,  H03K17/687

CPC classification number: H04B1/04 ,  H02M3/158 ,  H03K17/163 ,  H03K17/6872 ,  H03K19/0175 ,  H03M9/00

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.