公开(公告)号：US10979034B1

公开(公告)日：2021-04-13

申请号：US16012557

申请日：2018-06-19

Applicant: Xilinx, Inc.

Inventor： Kumar Rahul ,  Santosh Yachareni ,  Jitendra Kumar Yadav ,  Md Nadeem Iqbal ,  Teja Masina ,  Sourabh Swarnkar ,  Suresh Babu Kotha

IPC: H03K3/3562 ,  H03K3/012 ,  H03K3/037 ,  H03K19/0185 ,  H03K19/00

Abstract: A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.

公开(公告)号：US10411710B1

公开(公告)日：2019-09-10

申请号：US16211149

申请日：2018-12-05

Applicant: Xilinx, Inc.

Inventor： Shidong Zhou ,  Sree RKC Saraswatula ,  Jing Jing Chen ,  Teja Masina ,  Narendra Kumar Pulipati ,  Santosh Yachareni

IPC: H03K19/177

Abstract: An example read address generation circuit for a static random access memory (SRAM) cell includes an operational amplifier having a non-inverting input coupled to a reference voltage, a memory emulation circuit having an output coupled to an inverting input of the operational amplifier and a control input coupled to an output of the operational amplifier, and a multiplexer having a first input coupled to receive a constant read voltage, a second input coupled to the output of the operational amplifier, and an output coupled to supply a read address voltage to the SRAM cell.