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    CONTINUOUS TIME LINEAR EQUALIZATION (CTLE) ADAPTATION ALGORITHM ENABLING BAUD-RATE CLOCK DATA RECOVERY (CDR) LOCKED TO CENTER OF EYE
    1.
    发明申请
    CONTINUOUS TIME LINEAR EQUALIZATION (CTLE) ADAPTATION ALGORITHM ENABLING BAUD-RATE CLOCK DATA RECOVERY (CDR) LOCKED TO CENTER OF EYE 审中-公开

    公开(公告)号：WO2021096613A1

    公开(公告)日：2021-05-20

    申请号：PCT/US2020/054456

    申请日：2020-10-06

    Applicant: XILINX, INC.

    Inventor： WU, Zhaoyin D. ,  UPADHYAYA, Parag

    IPC: H04L25/03 ,  H04L7/00

    Abstract: Apparatus and associated methods relate to adapting a continuous time linear equalization circuit with minimum mean square error baud-rate clock and data recovery circuit to be able to lock to the center or near center of an eye diagram. In an illustrative example, a circuit may include an inter-symbol interference (ISI) detector configured to receive data and error samples, a summing circuit coupled to the output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voter configured to generate a vote in response to the average output and a predetermined threshold, and, an accumulator and code generator configured to generate a code signal in response to the generated vote. By introducing the moving average filter and the voter, a quicker way to lock to the center or near center of an eye diagram may be obtained.

    BUILT-IN EYE SCAN FOR ADC-BASED RECEIVER
    2.
    发明申请
    BUILT-IN EYE SCAN FOR ADC-BASED RECEIVER 审中-公开
    用于基于ADC的接收器的内置眼睛扫描

    公开(公告)号：WO2018080652A1

    公开(公告)日：2018-05-03

    申请号：PCT/US2017/051379

    申请日：2017-09-13

    Applicant: XILINX, INC.

    Inventor： ZHANG, Hongtao ,  WU, Zhaoyin D. ,  BORRELLI, Christopher J. ,  ZHANG, Geoffrey

    IPC: G01R31/02 ,  H04L43/02 ,  H04L7/00

    Abstract: An example method of performing an eye-scan in a receiver includes: generating (104) digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing (204) the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting (404) the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking (406) the plurality of equalization parameters, suspending (408) phase detection in the clock recovery, offsetting (410) the PI code, collecting (412) an output of the receiver, resuming (414) the phase detection in the clock recovery, and unlocking (414) the equalization parameters to perform the eye scan.

    Abstract translation: 在接收器中执行眼睛扫描的示例方法包括：基于采样时钟从输入到接收器的模拟信号生成（104）数字采样，所述采样时钟的相位相移 以基于相位内插器（PI）码的参考时钟; 基于所述接收器的多个均衡参数的第一均衡参数来均衡（204）所述数字样本; 对所述多个均衡参数进行适配（404）并且基于所述数字样本执行时钟恢复以生成所述PI码; （406）所述多个均衡参数，在所述时钟恢复中暂停（408）相位检测，偏移（410）所述PI代码，收集（412）所述接收器的输出，恢复（414） 时钟恢复中的相位检测，以及解锁（414）均衡参数以执行眼部扫描。

    PROGRAMMABLE DIGITAL SIGMA DELTA MODULATOR
    3.
    发明申请
    PROGRAMMABLE DIGITAL SIGMA DELTA MODULATOR 审中-公开

    公开(公告)号：WO2019231857A1

    公开(公告)日：2019-12-05

    申请号：PCT/US2019/034026

    申请日：2019-05-24

    Applicant: XILINX, INC

    Inventor： MEGAWER, Karim M. ,  UPADHYAYA, Parag ,  TURKER MELEK, Didem Z. ,  WU, Zhaoyin D.

    IPC: H03M3/00 ,  H03M7/36 ,  H03L7/197

    Abstract: An example sigma delta modulator (SDM) circuit includes a floor circuit (306), a subtractor (308) having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter (302) having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit (304) having an input coupled to the output of the floor circuit, and an adder (310) having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.

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