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公开(公告)号:JP2003235013A
公开(公告)日:2003-08-22
申请号:JP2002032434
申请日:2002-02-08
Applicant: YAMAHA CORP
Inventor: FUJISHIMA MASAKAZU
Abstract: PROBLEM TO BE SOLVED: To provide a video reproducing apparatus and a control method for the video reproducing apparatus capable of attaining effects such as cross fade without the need for provision of a plurality of decoders. SOLUTION: When receiving a video reception instruction, the video reproducing apparatus 40 decodes video encoding data for a fade-out part in the case of cross-fading video images before and after switching and stores the result into an HDD 43 for effects. In the case of reading the video encoded data from an HDD 41 for a video image, decoding the data by a decoder 42, and producing and outputting a video signal from the decoded video data, the decoded data for the fade-out part are read from the HDD 43 for effects, a video signal for cross-fade is produced and outputted from the decoded data and output data from the decoder 42. COPYRIGHT: (C)2003,JPO
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公开(公告)号:JP2002084599A
公开(公告)日:2002-03-22
申请号:JP2000273026
申请日:2000-09-08
Applicant: YAMAHA CORP
Inventor: TAMARU TAKUYA , OGITA MINORU , FUJISHIMA MASAKAZU , YAMADA MORIHITO
Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for reproducing sound of karaoke performance, or the like, in which sound can be reproduced while setting the direction of sound field appropriately with respect to the arrangement of speakers. SOLUTION: Speakers SP1-SP4 and a microphone 16 are arranged in a room 10. Accompaniment sound, surround sound of an accompanist, microphone sound and echo/reverb sound of microphone sound are fed through attenuator groups 20, 24, 28 and 32 to each speaker and delivered therefrom. A sound field direction setting section 40 sets the direction of a microphone from the central position 42a of a space 42 surrounded by speakers as the front direction of the sound field. A control section 44 controls attenuation of the attenuator groups 20, 24, 28 and 32 such that a sound field is formed in a direction set at the sound field direction setting section 40.
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公开(公告)号:JPH033976B2
公开(公告)日:1991-01-21
申请号:JP19732181
申请日:1981-12-08
Applicant: YAMAHA CORP
Inventor: FUJISHIMA MASAKAZU
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公开(公告)号:JPH0221685B2
公开(公告)日:1990-05-15
申请号:JP7069082
申请日:1982-04-27
Applicant: YAMAHA CORP
Inventor: FUJISHIMA MASAKAZU
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公开(公告)号:JPH023341B2
公开(公告)日:1990-01-23
申请号:JP19732081
申请日:1981-12-08
Applicant: YAMAHA CORP
Inventor: FUJISHIMA MASAKAZU
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公开(公告)号:JP2007087707A
公开(公告)日:2007-04-05
申请号:JP2005273712
申请日:2005-09-21
Applicant: Yamaha Corp , ヤマハ株式会社
Inventor: FUJISHIMA MASAKAZU
CPC classification number: Y02E60/12
Abstract: PROBLEM TO BE SOLVED: To provide a battery pack management system which can monitor a battery capacity of each single item of battery packs.
SOLUTION: A battery 100 has a memory 120 on which identification information such as a production number is written, and a remote control unit 10 reads the identification information of the installed battery 100 electrically. When the remote control unit 10 is charged by a charger 9, a charge/discharge sensor 119 of a battery connection 118 detects charging of the battery 100 and gives its information to a CPU 101. The CPU 101 updates the charge/discharge information stored in a RAM 103 for the applicable battery with the identification information and the charge/discharge information obtained.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 要解决的问题:提供一种电池组管理系统,其可以监测每个单个电池组的电池容量。 解决方案:电池100具有写入诸如生产编号的识别信息的存储器120,并且遥控单元10电气地读取安装的电池100的识别信息。 当遥控单元10被充电器9充电时,电池连接118的充电/放电传感器119检测电池100的充电并将其信息提供给CPU 101. CPU 101更新存储在其中的充电/放电信息 用于具有所获得的识别信息和充电/放电信息的适用电池的RAM 103。 版权所有(C)2007,JPO&INPIT
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公开(公告)号:JP2004096878A
公开(公告)日:2004-03-25
申请号:JP2002253690
申请日:2002-08-30
Applicant: Yamaha Corp , ヤマハ株式会社
Inventor: FUJISHIMA MASAKAZU
Abstract: PROBLEM TO BE SOLVED: To have no effect upon output voltage caused by a power supply unit even if instantaneous interruption occurs at a commercial power supply using a simple and low-cost structure. SOLUTION: This compensating circuit comprises an instantaneous interruption compensating circuit 50 on a forward stage of the power supply unit 10 which generates constant DC voltage from the voltage supplied to the input terminal 11. The circuit 50 includes a bridge diode 52 which rectifies AC voltage supplied from the commercial power supply for conversion into DC; and a capacitor 54 for holding the rectified voltage and supplying the held voltage to an input terminal 11 of the power supply unit 10. COPYRIGHT: (C)2004,JPO
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公开(公告)号:JP2002108372A
公开(公告)日:2002-04-10
申请号:JP2000301904
申请日:2000-10-02
Applicant: YAMAHA CORP
Inventor: FUJISHIMA MASAKAZU , OGITA MINORU , KAMIYA SHINGO
Abstract: PROBLEM TO BE SOLVED: To provide a KARAOKE device which can easily control whether or not music data can be played. SOLUTION: Even music data of managed songs which need not be permitted to be played by pieces of music and KARAOKE devices are stored on a hard disk similarly to music data of other KARAOKE songs. Then ROMs 20 stored with key data for allowing the managed songs to be played are manufactured by the managed songs and the KARAOKE devices and sets in a KARAOKE device to permit the managed songs to be played. Consequently, the KARAOKE device need not have media such as a CD-ROM by the managed songs and the copyright holders of the managed songs can physically manage the numbers of permitted cases by the ROMs 20.
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公开(公告)号:JP2005257832A
公开(公告)日:2005-09-22
申请号:JP2004066618
申请日:2004-03-10
Applicant: Yamaha Corp , ヤマハ株式会社
Inventor: FUJISHIMA MASAKAZU
Abstract: PROBLEM TO BE SOLVED: To prevent an indefinite-pitch performance sound from deteriorating in sound quality accompanying pitch change in a digital sound recording type musical performance reproducing device. SOLUTION: A hard disk 38 has a 1st recording track where digital sound recording data of indefinite-pitch performance sounds such as drum sounds and handclaps are recorded and a 2nd recording track where digital sound recording data of definite-pitch performance sounds such as stringed instrument sounds and wind instrument sound are recorded. Sound recording data of each recording track are compressed and encoded by, for example, the MP3 system. When the musical performance is reproduced, sound recording data of selected music are transferred from the disk 38 to a RAM 16, and the indefinite-pitch and definite-pitch sound recording data are processed through processing channels C 1 and C 2 . When a desired tempo change quantity or pitch change quantity is specified at an operation part 34, a pitch controller 30 or 33 performs pitch control, but a pitch controller 30 does not perform pitch control, thereby preventing the indefinite-pitch performance sounds from deteriorating in sound quality. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题:为了防止随着数字录音型音乐演奏再现装置中的音调变化的音质的不确定的音调性能下降。 解决方案:硬盘38具有第一记录轨道,其中记录了诸如鼓声和手指之类的无限间距表现声音的数字声音记录数据,以及第二记录轨道,其中确定音调性能的数字声音记录数据如下 作为弦乐器声音和乐器声音被记录。 每个记录轨道的声音记录数据被例如MP3系统压缩和编码。 当再现演奏时,所选择的音乐的录音数据从盘38传送到RAM16,并且通过处理通道C
1 SB>处理不定音调和确定音调的声音记录数据。 和C 2 SB>。 当在操作部分34中指定了期望的速度变化量或音调变化量时,俯仰控制器30或33执行俯仰控制,但是俯仰控制器30不执行俯仰控制,从而防止了不确定的俯仰性能声音恶化 音质。 版权所有(C)2005,JPO&NCIPI -
公开(公告)号:JPS62223817A
公开(公告)日:1987-10-01
申请号:JP6794386
申请日:1986-03-26
Applicant: YAMAHA CORP
Inventor: FUJISHIMA MASAKAZU
IPC: G11B7/00 , G11B7/0037 , G11B7/004 , G11B7/09 , G11B20/18
Abstract: PURPOSE:To detect a drop-out in the condition of an original signal and to simplify a circuit constitution without executing the signal processing such as an FM demodulation by comparing two sum signal waveforms and detecting the drop-out. CONSTITUTION:When a drop-out occurs and the period of a part of a sum signal A+C is short, for D flip-flop circuits 90 and 92, the fall zero cross of the A+C of the sum signal is inputted only to a clear input CL two times continuously while the rise zero cross of the B+D of the sum signal is inputted, and therefore, the D flip-flop circuit 92 is not set. Since for a D flip-flop circuit 94, the rise zero cross of the sum signal A+C is inputted to a clock input CK two times continuously while the fall zero cross of the sum signal B+D is inputted to the clear input CL, a D flip-flop circuit 96 is set by the second input and a drop-out detecting signal is outputted from an OR circuit 98.
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