公开(公告)号：HK1051436A1

公开(公告)日：2003-08-01

申请号：HK03103561

申请日：2003-05-20

Applicant: YAMAHA CORP

Inventor： NATSUME KIYOSHI ,  NAITO HIROSHI

IPC: H01C20060101 ,  H01L21/30 ,  C03C17/36 ,  C23F1/26 ,  G01K20060101 ,  H01C7/00 ,  H01C17/075 ,  H01L20060101 ,  H01L21/02 ,  H01L27/01 ,  H05K3/04

Abstract: A sacrificial film is formed on a substrate and a mask layer is formed on the sacrificial film. An opening having a predetermined pattern is formed through the mask layer. The sacrificial film exposed in the opening is removed to form a cave broader than the opening on the substrate. A noble metal thin film is deposited on the whole substrate surface. The sacrificial film 12 is dissolved and removed to form a noble metal thin film pattern.

公开(公告)号：JP2011138993A

公开(公告)日：2011-07-14

申请号：JP2009299261

申请日：2009-12-29

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KURIHARA SHUNSUKE ,  NATSUME KIYOSHI

IPC: H01L21/822 ,  H01L21/285 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, capable of forming a thin-film resistor having a small TCR (temperature coefficient of resistance) value and formed of a TaN film ensuring a practically necessary film thickness while preventing TaN film damage in forming a wiring of the resistor.
SOLUTION: A first interlayer dielectric is formed on a semiconductor substrate having a semiconductor element formed thereon, and a tantalum nitride film is formed on the first interlayer dielectric by first sputtering at a substrate temperature from a normal temperature to 400°C with a nitride gas partial pressure ratio of 3-10% in a reaction gas. After that, a via hole reaching the tantalum nitride film is formed by wet etching on the second interlayer dielectric formed on the first interlayer dielectric, a metal film is deposited by second sputtering to form the metal film in the via hole, and a via connected to the tantalum nitride film is formed.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种半导体器件的制造方法，其能够形成具有小的TCR（电阻温度系数）值的薄膜电阻器，并且由确保实际上必需的膜厚度的TaN膜形成， 防止在形成电阻器的布线时损坏TaN膜。 解决方案：在其上形成有半导体元件的半导体衬底上形成第一层间电介质，并且在基板温度从常温到400℃下通过第一次溅射在第一层间电介质上形成氮化钽膜， 在反应气体中氮化物气体分压比为3-10％。 之后，通过在形成在第一层间电介质上的第二层间电介质上进行湿式蚀刻形成到达氮化钽膜的通孔，通过第二溅射沉积金属膜，以在通孔中形成金属膜，并且通孔连接 形成氮化钽膜。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JPH0661423A

公开(公告)日：1994-03-04

申请号：JP21181292

申请日：1992-08-07

Applicant: YAMAHA CORP

Inventor： NATSUME KIYOSHI

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L27/06

Abstract: PURPOSE:To simply and easily manufacture a semiconductor device wherein individual elements are included by a method wherein a capacitor element, a resistor element and a gate electrode are formed in the same manufacturing process. CONSTITUTION:A capacitor film 1 by a single-layer oxide film is formed on the surface of a polysilicon layer 2. The surface of the capacitor film 1 is coated with a photoresist. Out of the coated photoresist, only a part corresponding to the capacitor film for a capacitor element C and only a part corresponding to a resistor element R are left, and other parts are etched and removed. Then, the capacitor film 1 is etched by making use of the left photoresist as a mask material. As a result, out of the capacitor film 1, only the part to be used as the capacitor film for the capacitor element C and only the part corresponding to the resistor element R are left, and the capacitor film in other parts is removed. At this time, when the capacitor film 1 is etched, the surface treatment of the polysilicon layer 2 to be used as the lower-layer part of a gate electrode for a MOSFET is executed. Thereby, the etching of the capacitor film 1 is finished, and photoresists 5a, 5b on the capacitor film 1 are removed.

公开(公告)号：JPH07122657A

公开(公告)日：1995-05-12

申请号：JP28875093

申请日：1993-10-25

Applicant: YAMAHA CORP

Inventor： NATSUME KIYOSHI

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To bring an FET into interrupted state easily and positively while minimizing the lowering of operating speed by forming an interrupting region having a conductivity type opposite to that of a source region or a drain region at least on one side of a gate electrode layer through an interruption trench. CONSTITUTION:After forming a gate electrode layer 14 on the surface of a semiconductor substrate 10 through a gate insulation film 12, N type source and drain regions 18, 20 are formed, respectively, on the opposite sides of the gate electrode layer 14. The surface of the substrate 10 is then selectively etched using the laminate of the gate electrode layer 14 and the gate insulation film 12, along with a resist layer, as a mask thus forming interruption trenches 24, 26, respectively, on the source side and drain side of the gate electrode layer 14. Subsequently, P type interruption regions 28, 30 are formed through the interruption trenches 24, 26 by selective ion implantation using a mask. This method allows to bring a gate insulated FET into interrupted state easily and positively without increasing the capacity of PN junction significantly.

公开(公告)号：JPH05102404A

公开(公告)日：1993-04-23

申请号：JP29235991

申请日：1991-10-11

Applicant: YAMAHA CORP

Inventor： MAKINO TOUHACHI ,  NATSUME KIYOSHI

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/088 ,  H01L27/112 ,  H01L29/78

Abstract: PURPOSE:To shorten a time in manufacturing from a channel doping marking step to a completion step for a semiconductor device having a MOS-type transistor. CONSTITUTION:After a field insulating film 12 is formed on the surface of a semiconductor substrate 10, a MOS transistor is formed in a device hole of the insulating film 12. The MOS transistor comprises a field insulating film 14, a gate electrode layer 22, and source and drain regions 24S and 24D. An insulating film layer 25 is formed to cover the MOS transistor and the insulating film 12. Then, a resist layer 26, which has a first hole 26a for making a mark and a second hole 26b for ion implantation, is formed on the insulating layer 25. Impure ions are implanted selectively through the second hole 26b to the surface of the substrate, and thereby the channel characteristics are determined. Before or after this ion implantation step, the insulating layer 25 is etched selectively through the first hole 26a to form a marking part 26A.

公开(公告)号：JP2003258327A

公开(公告)日：2003-09-12

申请号：JP2002223613

申请日：2002-07-31

Applicant: YAMAHA CORP

Inventor： NATSUME KIYOSHI ,  NAITO HIROSHI

IPC: C23C14/14 ,  H01L21/28 ,  H01L21/3205 ,  H01L37/00

Abstract: PROBLEM TO BE SOLVED: To obtain a formation method in which the inclination of a side wall of a noble metal film pattern obtained in forming a noble metal film pattern such as of platinum can be reproductively controlled, a good quality film can be obtained without being influenced by a gas generated from a resist, the noble metal film pattern is prevented from being attached with foreign materials, being damaged, or being lowered in its yield, a base is prevented from excessively polished, and mechanical strength is prevented from lowering. SOLUTION: A sacrificial film 12 is formed on a substrate 11, and a mask layer 13 is further formed thereon. Then an opening 15 of a given pattern is formed on the mask layer 13, and the sacrificial film 12 exposed from the opening 15 is removed so as to form a hollow portion 16 on the substrate 11, which is larger than the opening 15. Subsequently, a noble metal film is deposited on the whole surface of the substrate 11, followed by melting and removing the sacrificial film 12, thereby forming the noble metal film pattern 18. COPYRIGHT: (C)2003,JPO

公开(公告)号：JPH05121406A

公开(公告)日：1993-05-18

申请号：JP23202591

申请日：1991-09-11

Applicant: YAMAHA CORP

Inventor： KURIHARA SHUNSUKE ,  NATSUME KIYOSHI

IPC: H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522

Abstract: PURPOSE:To maintain an excellent flatness and to prevent cracking when baking at high temperature. CONSTITUTION:An organic coating glass 4 is applied thick on the surface of a silicon substrate 1. Then, it is baked and removed by etching except for the portion between gate electrodes 2 on the silicon substrate 1. Then, the organic coating glass 4 is baked at a temperature higher than the previous baking process.

公开(公告)号：JP2002333468A

公开(公告)日：2002-11-22

申请号：JP2002032565

申请日：2002-02-08

Applicant: YAMAHA CORP ,  DENSO CORP

Inventor： SUZUKI TOSHINAO ,  MOCHIZUKI OSAMU ,  NATSUME KIYOSHI ,  MURATA YUICHIRO ,  TOYODA INEO ,  SUZUKI YASUTOSHI ,  UENOYAMA HIROBUMI

IPC: G01R33/09 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To prevent a crack from being generated in a chip when the magnetometric sensor chip is fixed to a support member such as a lead frame via a heating adhesive layer. SOLUTION: Magnetic resistance elements R1 , R2 of which each comprises one or plural serial magnetic tunnel effect elements are formed on an insulating surface of a substrate 10 such as a slicon substrate. The magnetic resistance elements R1 , R2 are series-connected via an insulation film 30 by a wiring layer 32 formed on the substrate surface. The magnetic resistance elements R1 , R2 and the wiring layer 32 are covered to form a passivation insulation film 34. A magnetic shielding layer 42 such as a Ni-Fe alloy layer is formed to cover the element R2 via an organic film 36 for thermal stress relaxation such as a polyimide film. The magnetometric sensor chip 10 including the elements R1 , R2 and the like is separated from a wafer, and the chip 10 is thereafter fixed to the lead frame via an Ag paste layer by heat treatment. The Ni-Fe alloy layer having 69% or less of Ni content is preferably used as the magnetic shield layer 42.

公开(公告)号：JPH0621188A

公开(公告)日：1994-01-28

申请号：JP33093391

申请日：1991-12-13

Applicant: YAMAHA CORP

Inventor： NATSUME KIYOSHI

IPC: H01L21/66 ,  H01L21/301 ,  H01L21/3205 ,  H01L21/78 ,  H01L23/52 ,  H01L23/544

Abstract: PURPOSE:To avoid the possibility of a short-circuit between the pins, leads, bonding wires, bonding pads, etc., of an IC or LSI completely by a method wherein the lengths of metal scraps produced from test electrodes by dicing are made to be shorter than distances between the above mentioned parts CONSTITUTION:A plurality of test chips are formed on a semiconductor wafer together with a plurality of IC's and LSI's. A plurality of the test chips are formed on scribe lines 10 along which a plurality of the IC's and LSI's are cut into a plurality of semiconductor chips. A plurality of slits 11 which cross the scribe line 10 are provided in the test electrode 9 of each test chip with which a probe for electrical measurement is brought into contact with required intervals D.