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公开(公告)号:JPH08274257A
公开(公告)日:1996-10-18
申请号:JP7694096
申请日:1996-03-29
Applicant: YAMAHA CORP
Inventor: TAKAHASHI TOSHIYUKI , SUGA SHIGERU , MAKINO TOUHACHI
IPC: H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L27/092
Abstract: PURPOSE: To suppress the increase in manufacturing cost, to suppress complexity of manufacturing process and to prevent the deterioration in electric characteristics of a capacitor element, etc., by a method wherein the second and the third conductive layers are etched using a mask member as an etching mask, and the upper electrode and the lower electrode of the capacitor element and the gate electrode of a MOSFET are formed simultaneously. CONSTITUTION: A polysilicon layer 2 is deposited on the gate oxide film 4 formed on the surface of a semiconductor substrate 10. A dielectric film 1, to be used as a capacitor film, is conformaly deposited on the surface of the polysilicon layer 2. The second layer of polysilicon layer 6a is deposited on the dielectric film 1 using a CVD method. The polysilicon layer 6a and the dielectric film 1 are selectively removed, and a laminated structure is left on the region where a capacitor C and a resistance element R are formed. A rhigh melting point metal silicide layer 6 is deposited, and polycide etching is performed. The high melting point silicide layer 6b and the polysilicon layer 6a are selectively etched, and the upper electrode L2 of the capacitor element C and a gate electrode G are formed simultaneously.
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公开(公告)号:JPH0945867A
公开(公告)日:1997-02-14
申请号:JP21680195
申请日:1995-08-02
Applicant: YAMAHA CORP
Inventor: TAKAHASHI TOSHIYUKI , MAKINO TOUHACHI , MAEJIMA TOSHIO
IPC: H01L23/12 , H01L21/265 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/78
Abstract: PROBLEM TO BE SOLVED: To enable MOS transistors of different threshold values to be easily integrated into a semiconductor device by a method wherein ion implantation conditions are set conforming to both a polysilicon gate structure and a polycide gate structure. SOLUTION: A gate oxide film 3 is formed on a silicon substrate 1. A gate electrode G1 is formed in a region of a D-type MOS transistor Q1 on the gate oxide film 3 by patterning a first polysilicon film 4, and a polycide gate electrode G2 of laminated structure composed of the first polysilicon film 4 and a silicide film 8 is formed in a region of an E-type MOS transistor Q2 by patterning. An ion implantation process is carried out using the gates G1 and G2 as a mask for forming an LDD structure. At this point, the conditions for ion implantation are so selected as to enable ions to penetrate through the polysilicon gate electrode G1 on a D-type MOS transistor Q1 side but not to penetrate through the polycide gate electrode G2 on an E-type MOS transistor Q2 to form ion implanted layers.
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公开(公告)号:JPH05102404A
公开(公告)日:1993-04-23
申请号:JP29235991
申请日:1991-10-11
Applicant: YAMAHA CORP
Inventor: MAKINO TOUHACHI , NATSUME KIYOSHI
IPC: H01L21/8234 , H01L21/336 , H01L21/8246 , H01L27/088 , H01L27/112 , H01L29/78
Abstract: PURPOSE:To shorten a time in manufacturing from a channel doping marking step to a completion step for a semiconductor device having a MOS-type transistor. CONSTITUTION:After a field insulating film 12 is formed on the surface of a semiconductor substrate 10, a MOS transistor is formed in a device hole of the insulating film 12. The MOS transistor comprises a field insulating film 14, a gate electrode layer 22, and source and drain regions 24S and 24D. An insulating film layer 25 is formed to cover the MOS transistor and the insulating film 12. Then, a resist layer 26, which has a first hole 26a for making a mark and a second hole 26b for ion implantation, is formed on the insulating layer 25. Impure ions are implanted selectively through the second hole 26b to the surface of the substrate, and thereby the channel characteristics are determined. Before or after this ion implantation step, the insulating layer 25 is etched selectively through the first hole 26a to form a marking part 26A.
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