公开(公告)号：JPH09148529A

公开(公告)日：1997-06-06

申请号：JP32973195

申请日：1995-11-24

Applicant: YAMAHA CORP

Inventor： SUGA SHIGERU

IPC: H01L21/822 ,  B05D5/12 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To reduce the occupation area of a resistor and improve precision of resistance formation. SOLUTION: Resistance material like poly Si is deposited on an insulating surface of a substrate and patterned, and resistance layers 14a-14c are arranged and formed almost in parallel. Resistance material like poly Si is deposited via insulating films 16 so as to fill spaces between adjacent resistance layers, and etched back. Thus resistance layers 18a-18c are formed in the respective spaces. After an insulating film 16 is formed covering the layers 14a-14c, 18a-18c, a connecting hole is formed in the insulating film 16, and conducting member is deposited and patterned. Thereby the conducting layers 22a-22e are so formed that the layers 14a, 18a, 14b, 18b, 14c, 18c are connected in series.

公开(公告)号：JPH08274257A

公开(公告)日：1996-10-18

申请号：JP7694096

申请日：1996-03-29

Applicant: YAMAHA CORP

Inventor： TAKAHASHI TOSHIYUKI ,  SUGA SHIGERU ,  MAKINO TOUHACHI

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

Abstract: PURPOSE: To suppress the increase in manufacturing cost, to suppress complexity of manufacturing process and to prevent the deterioration in electric characteristics of a capacitor element, etc., by a method wherein the second and the third conductive layers are etched using a mask member as an etching mask, and the upper electrode and the lower electrode of the capacitor element and the gate electrode of a MOSFET are formed simultaneously. CONSTITUTION: A polysilicon layer 2 is deposited on the gate oxide film 4 formed on the surface of a semiconductor substrate 10. A dielectric film 1, to be used as a capacitor film, is conformaly deposited on the surface of the polysilicon layer 2. The second layer of polysilicon layer 6a is deposited on the dielectric film 1 using a CVD method. The polysilicon layer 6a and the dielectric film 1 are selectively removed, and a laminated structure is left on the region where a capacitor C and a resistance element R are formed. A rhigh melting point metal silicide layer 6 is deposited, and polycide etching is performed. The high melting point silicide layer 6b and the polysilicon layer 6a are selectively etched, and the upper electrode L2 of the capacitor element C and a gate electrode G are formed simultaneously.

公开(公告)号：JP2004153297A

公开(公告)日：2004-05-27

申请号：JP2004004980

申请日：2004-01-13

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： SUGA SHIGERU

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing the number of additional steps in a manufacturing process and having a MOS transistor in an active region and a capacitor on a filed oxide film.
SOLUTION: The semiconductor device comprises: a semiconductor substrate having a main surface; a field oxide film formed on the main surface of the semiconductor substrate and defining an active region; an insulating gate structure formed on the active region and containing a gate oxide film and a first polycrystalline Si layer; a capacitor lower electrode formed on the field oxide film and containing a second polycrystalline Si layer having the thickness almost the same as that of the first polycrystalline Si layer; an insulating film formed on the surfaces of the first polycrystalline Si layer and the second polycrystalline Si layer; a sidewall conductive material region formed only on the sidewall of the insulating film on the surface of the first polycrystalline Si layer and the second polycrystalline Si layer; and a capacitor upper electrode which is a layer formed on the upper surface of the second polycrystalline Si layer and made of the same material as that of the conductive region, and having a polysilicon layer and a layer formed thereon and made of a high melting point metal or its silicide.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JPS63132434A

公开(公告)日：1988-06-04

申请号：JP27937886

申请日：1986-11-22

Applicant: YAMAHA CORP

Inventor： YOKOI KATSUYUKI ,  SUGA SHIGERU ,  FUJIOKA TOSHIO

IPC: H01L21/318 ,  H01L23/29 ,  H01L23/31 ,  H01L29/78

Abstract: PURPOSE:To reduce the deterioration in characteristics due to hot carrier implantation doing no damage to interconnection layers by a method wherein silicon bonding hydrogen content contained in silicon nitride film covering the surface is specified not to exceed specific value. CONSTITUTION:A protective film 28 comprising silicon nitride to cover interconnection layers 24, 26 is formed on an interlayer insulating film 22. The protective film 28 is formed e.g. by ECR plasma CVD prodess so that the Si-H content may not exceed 5X10 (each/cm ). Thus, the hydrogen level reaching a gate insulating film 14 is reduced to achieve the reducing effect of deterioration in characteristics. Through these procedures, the deterioration in characteristics due to hot carrier implantation can be reduced doing no damage to the interconnection layers 24, 26.

公开(公告)号：JP2000349166A

公开(公告)日：2000-12-15

申请号：JP2000135507

申请日：2000-05-09

Applicant: YAMAHA CORP

Inventor： TAKAHASHI TOSHIYUKI ,  SUGA SHIGERU ,  MAKINO TOHACHI

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a MOSFET and a capacitive element without excessively complicating manufacturing processes, increasing a manufacturing cost, and deteriorating the MOSFET and the capacitive element in electrical properties. SOLUTION: A gate insulating film is formed on the surface of a semiconductor substrate 100. A capacitive element where a first electrode layer, a dielectric layer, a second electrode layer, and a third electrode layer of metal or metal silicide are laminated in this sequence is formed in a certain region of the surface of the semiconductor substrate 100. The first and second electrode layer are formed of the same material. A gate electrode of laminated structure composed of a first gate layer deposited at the same time with the first electrode layer and second gate layer deposited at the same time with the third electrode layer is formed in a region of a gate insulating film. An interlayer insulating film is formed on the semiconductor substrate 100 so as to cover the capacitive element and the gate electrode, and a wiring is provided thereon.

公开(公告)号：JPH08330511A

公开(公告)日：1996-12-13

申请号：JP13079395

申请日：1995-05-29

Applicant: YAMAHA CORP

Inventor： SUGA SHIGERU

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06

Abstract: PURPOSE: To realize a semiconductor device with a MOS transistor at an active region and a capacitor on a field oxide film by making the side wall spacer of the MOS transistor of polycrystalline Si and reducing an addition process. CONSTITUTION: A field oxide film 2, a gate oxide film 3, and a polycrystalline Si layer 4 are formed on Si semiconductor substrate 1, etched with resist patterns 5a and 5b masks, polycrystalline Si layers 4a and 4b which become capacitor lower electrodes are formed, and an LDD region 6 of the MOS transistor is formed by implanting ions. Then, silicon oxide films 9a and 9b are formed on the polycrystalline Si layers 4a and 4b and a second polycrystalline Si layer 11 is deposited on the substrate, ions are implanted, and etched with a resist pattern 12. Then, polycrystalline Si regions 11a and 11b remain as a side wall spacer on the side wall of the gate electrode 4a and that of the capacitor lower electrode 4b and the polycrystalline Si layer 11 which becomes a capacitor upper electrode also remains, thus realizing a semiconductor device.