公开(公告)号：WO1996021968A1

公开(公告)日：1996-07-18

申请号：PCT/US1995012415

申请日：1995-09-29

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  PETERSON, Kevin, H. ,  MASSALIN, Henry

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H03D03/00

CPC classification number: H03D3/007 ,  H03D2200/005 ,  H03D2200/0052 ,  H03D2200/0062 ,  H03D2200/0072

Abstract: A digital FM demodulator and method for determining phase changes in highly oversampled complex FM digital signals is described. In a first embodiment the FM signal is oversampled with respect to the frequency of its associated modulating signal. In this embodiment a first digital processing stage delays and conjugates the original FM signal. This delayed conjugated original FM signal is then multiplied with the original FM signal to generate a second signal that represents the changes in the phase between samples of the original FM signal. A second processing stage then delays and conjugates the second signal. The delayed conjugated second signal is then multiplied with the original second signal to generate a third signal that represents changes in the phase between samples of the second signal. The imaginary component of the third signal is passed through a digital integrator which outputs the phase changes of the original FM signal. In a second embodiment, the highly oversampled signal is oversampled with respect to the deviation frequency of its associated modulating signal. In this embodiment the center frequency of the original FM signal is frequency shifted to approximately zero frequency. This frequency shifted signal is then delayed and conjugated. The delayed conjugated shifted signal is then multiplied with the original frequency shifted signal; yielding an output signal where the imaginary portion of the output signal is equal to the phase changes of the original FM signal.

Abstract translation: 描述了用于确定高度过采样的复数FM数字信号中的相位变化的数字FM解调器和方法。 在第一实施例中，FM信号相对于其相关调制信号的频率被过采样。 在该实施例中，第一数字处理级延迟并共轭原始FM信号。 然后将该延迟的共轭原始FM信号与原始FM信号相乘以产生表示原始FM信号的样本之间的相位变化的第二信号。 第二处理级然后延迟并共轭第二信号。 然后将延迟的共轭第二信号与原始第二信号相乘以产生表示第二信号的样本之间的相位变化的第三信号。 第三信号的虚分量通过数字积分器，该数字积分器输出原始FM信号的相位变化。 在第二实施例中，高度过采样的信号相对于其相关调制信号的偏差频率被过采样。 在这个实施例中，原始FM信号的中心频率被频移到大致零频率。 然后，该频移信号被延迟并共轭。 然后将延迟的共轭移位信号与原始频移信号相乘; 产生输出信号，其中输出信号的虚部等于原始FM信号的相位变化。

公开(公告)号：WO1996003807A1

公开(公告)日：1996-02-08

申请号：PCT/US1995009349

申请日：1995-07-25

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  MOSTYN, Graham, Y. ,  HERNDON, William, H. ,  MOUSSOURIS, John, P. ,  ROBINSON, Timothy, B. ,  ROSSEEL, Geert, P.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H03K19/0185

CPC classification number: H03K19/0013 ,  H03K19/018507

Abstract: The present invention is an improvement of a digital topology including a logic block portion and a buffer portion. The improved buffer portion of the present invention is implemented with first and second parallel, same conductivity type transmission gates. The transmission gates couple either a first (V1) or second (V2) voltage onto the output of the buffer (55) in response to a logic signal originating from the logic block portion. The first (V1) and second (V2) voltages are selected to be relatively close in magnitude such that the peak-to-peak voltage of the digital output signal seen on the output of the buffer is relatively small. As a result, power consumption for charging the output of the buffer is minimized. In addition, the parallel transmission gates only consume power while charging the output of the buffer so that quiescent power consumption of the buffer is eliminated. Quiescent power dissipation is also eliminated in certain types of logic block designs that include logic gates having constant current sources. This is achieved by enabling the current sources with a pulse signal. The pulse width and magnitude of the pulse signal is selected to allow a latched sense amplifier to sense valid data from the output of the logic block portion during a specified interval. After valid data is sensed, the logic blocks's current sources are disabled, and the logic block portion no longer consumes any power. The sense amplifier is enabled for intervals long enough to capture the data from the logic block and drive the transmission gates with the data. In this configuration, none of the elements in the topology dissipate quiescent power since none of them are constantly operating.

Abstract translation: 本发明是包括逻辑块部分和缓冲部分的数字拓扑的改进。 本发明的改进的缓冲部分由第一和第二平行的相同导电类型的传输门来实现。 响应于源自逻辑块部分的逻辑信号，传输门将第一（V1）或第二（V2）电压耦合到缓冲器（55）的输出上。 第一（V1）和第二（V2）电压被选择为相对接近于幅度，使得在缓冲器的输出端上看到的数字输出信号的峰 - 峰电压相对较小。 结果，对缓冲器的输出进行充电的功耗最小化。 此外，并行传输门仅在缓冲器的输出充电时消耗功率，从而消除了缓冲器的静态功耗。 在包括具有恒定电流源的逻辑门的某些类型的逻辑块设计中也消除了静态功耗。 这是通过使能脉冲信号的电流源实现的。 选择脉冲信号的脉冲宽度和幅度以允许锁存的读出放大器在指定的间隔期间从逻辑块部分的输出检测有效数据。 在检测到有效数据之后，逻辑块的当前源被禁用，并且逻辑块部分不再消耗任何电力。 读出放大器使能间隔足够长的时间来捕获来自逻辑块的数据，并用数据驱动传输门。 在这种配置中，拓扑中的任何元件都不会消耗静态功耗，因为它们都不会持续运行。

公开(公告)号：WO1993014445A1

公开(公告)日：1993-07-22

申请号：PCT/US1993000456

申请日：1993-01-15

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  CHEN, Jang, Fung ,  MATTHEWS, James, A.

IPC: G03F09/00

CPC classification number: G03F1/36 ,  G03F7/70433 ,  G03F7/70441

Abstract: An improvement for reducing proximity effects comprised of additional lines, referred to as intensity leveling bars, into the mask pattern. The leveling bars perform the function of adjusting the edge intensity gradients of isolated edges in the mask pattern, to match the edge intensity gradients of densely packed edges. Leveling bars are placed parallel to isolated edges such that intensity gradient leveling occurs on all isolated edges of the mask pattern. In addition, the leveling bars are designed to have a width significantly less than the resolution of the exposure tool. Therefore, leveling bars that are present in the mask pattern produce resist patterns that completely developed away when a nominal exposure energy is utilized during exposure of photoresist.

公开(公告)号：WO2005008410A3

公开(公告)日：2005-01-27

申请号：PCT/US2004/022126

申请日：2004-07-12

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

IPC: G06F12/00

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

公开(公告)号：WO1998004970A1

公开(公告)日：1998-02-05

申请号：PCT/US1997012651

申请日：1997-07-21

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  LAIDIG, Thomas, L.

IPC: G06F09/00

CPC classification number: G06F17/5081

Abstract: A system for processing geometry which reduces the amount of memory spaces while improving the processing speed. The system delivers vertices in sequence to a vertex queue (70) so that data in the vertex queue is freed as it is delivered and only minimal intermediate results are stored. By this incremental evaluation, less memory space is needed. In another aspect of the invention the vertices are maintained in the proper sequence so that sorting operation can be eliminated. A sorted vertex queue (70) and an unsorted vertex list (72) are utilized so that resorting of the entire vertex list may be prevented. In addition, a compressed format (34) for storing geometry is utilized based on the fact that much information can be rederived from a sorted and reduced vertex queue.

Abstract translation: 一种用于处理几何的系统，其在提高处理速度的同时减少存储空间的量。 系统将顶点顺序传递到顶点队列（70），以便顶点队列中的数据在传递时释放，只存储最小的中间结果。 通过这种增量评估，需要更少的内存空间。 在本发明的另一方面中，顶点以适当的顺序保持，从而可以消除排序操作。 利用排序的顶点队列（70）和未排序的顶点列表（72），从而可以防止整个顶点列表的撤回。 此外，基于可以从排序和缩小的顶点队列重新获取大量信息的事实，利用用于存储几何的压缩格式（34）。

公开(公告)号：WO1996023353A1

公开(公告)日：1996-08-01

申请号：PCT/US1995015219

申请日：1995-11-21

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CORRY, Alan, G.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H03H17/06

CPC classification number: H03H17/0275 ,  H03H17/06

Abstract: A compact FIR filter uses one or both of a compact address sequencer and a compact multiplier/accumulator. The address sequencer exploits certain symmetry properties existing between different phases of a polyphase FIR filter in order to reduce coefficient storage and simplify address sequencing. The multiplier/accumulator is capable of performing two multiply/accumulate operations per clock cycle, avoiding in certain instances the need to add a second multiplier/accumulator. The area required to realize an FIR filter for performing real-time filter is therefore reduced.

Abstract translation: 紧凑型FIR滤波器使用紧凑型地址排序器和紧凑型乘法器/累加器中的一个或两者。 地址序列器利用多相FIR滤波器的不同相之间存在的某些对称性，以减少系数存储并简化地址排序。 乘法器/累加器能够在每个时钟周期执行两次乘法/累加操作，避免在某些情况下需要添加第二个乘法器/累加器。 因此，实现用于执行实时滤波器的FIR滤波器所需的面积减少。

公开(公告)号：WO1996017287A1

公开(公告)日：1996-06-06

申请号：PCT/US1995012416

申请日：1995-09-29

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CORRY, Alan, G. ,  SUTHERLAND, Robert, A.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F01/03

CPC classification number: H03C3/00 ,  G06F1/0328

Abstract: A direct digital synthesizer (DDS) for generating a waveform generates a sequence of n-bit phase signals representing phase of the waveform, wherein n is an integer greater than zero. Each n-bit phase signal comprises a phase estimate signal and a phase error signal. The phase estimate signal comprises a most-significant m bits of the n-bit quantity (0

Abstract translation: 用于产生波形的直接数字合成器（DDS）产生表示波形相位的n位相位信号的序列，其中n是大于零的整数。 每个n位相位信号包括相位估计信号和相位误差信号。 相位估计信号包括n比特量（0

公开(公告)号：WO1995001672A1

公开(公告)日：1995-01-12

申请号：PCT/US1994004900

申请日：1994-05-02

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MICHEL, Jean, Yves

IPC: H03M01/36

CPC classification number: H03M1/204 ,  H03M1/365

Abstract: A two-stage flash analog-to-digital signal converter is described. The first stage has a voltage divider network and a set of amplifiers that perform an initial interpolation. The initial interpolation results are directly coupled, i.e., no resistive or capacitive elements, to a second stage comprising a set of comparators having multiple inputs. The multiple inputs of the second stage comparators are weightily coupled to the first stage amplifiers in a manner so as to cause the second stage comparators to generate a digital representation of the analog signal.

Abstract translation: 描述了两级​​闪存模数转换器。 第一级具有分压网络和一组执行初始插值的放大器。 初始插值结果直接耦合到包括具有多个输入的一组比较器的第二级的电阻或电容元件。 第二级比较器的多个输入以这样的方式重叠耦合到第一级放大器，以便使第二级比较器产生模拟信号的数字表示。

公开(公告)号：WO1993020482A1

公开(公告)日：1993-10-14

申请号：PCT/US1993003126

申请日：1993-03-29

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  CHEN, Jang, Fung ,  MATTHEWS, James, A.

IPC: G03F07/20

CPC classification number: G03F7/70466 ,  G03F7/2022

Abstract: A method of printing a sub-resolution device feature (16) having first and second edges spaced in close proximity to one another on a semiconductor substrate (20) includes the steps of first depositing a radiation-sensitive material on the substrate, then providing a first mask image segment (11) which corresponds to the first edge. The first mask image segment is then exposed with radiation (10) using an imaging tool (12) to produce a first pattern edge gradient (14). The first pattern edge gradient defines the first edge of the feature in the material. A second mask image segment (13) is then provided corresponding to the second feature edge. This second mask image segment is exposed to radiation (10) to produce a second pattern edge gradient (17) which defines the second edge of the feature. Once the radiation-sensitive material has been developed, the two-dimensional feature is reproduced on the substrate.

Abstract translation: 印刷具有在半导体衬底（20）上彼此靠近彼此间隔开的第一和第二边缘的子分辨率器件特征（16）的方法包括以下步骤：首先在衬底上沉积辐射敏感材料，然后提供 第一掩模图像段（11），其对应于第一边缘。 然后使用成像工具（12）用辐射（10）将第一掩模图像段曝光以产生第一图案边缘梯度（14）。 第一个图案边缘渐变定义材料中特征的第一个边缘。 然后对应于第二特征边缘提供第二掩模图像段（13）。 该第二掩模图像段暴露于辐射（10）以产生限定特征的第二边缘的第二图案边缘梯度（17）。 一旦辐射敏感材料已经开发出来，二维特征就在基片上再现。

公开(公告)号：WO1993008599A1

公开(公告)日：1993-04-29

申请号：PCT/US1992008905

申请日：1992-10-19

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: H01L23/00

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/732 ,  Y10S148/01

Abstract: A bipolar transistor having an emitter (25), a base (31), and a collector (30) includes an intrinsic base (33) region having narrow side areas (p-) and a wider central area (37). The side areas are located adjacent to the extrinsic base region (31), while the central area (37) is disposed underneath the emitter (25). The lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region (31) and the central area (37) are relatively high compared to the doping concentration of the narrow side areas (p-) of the intrinsic base (33). The combination of the narrow side areas (p-) and the lateral base doping profile constrains the depletion region within the base thereby lowering punch-through voltage of the transistor without loss of beta.

Abstract translation: 具有发射极（25），基极（31）和集电极（30）的双极晶体管包括具有窄侧面积（p-）和较宽中心区域（37）的本征基极（33）区域。 侧面区域邻近外部基极区域（31）定位，而中心区域（37）设置在发射器（25）的下方。 定制基底的横向掺杂分布，使得非本征区域（31）和中心区域（37）中的掺杂浓度相对于本征基底的窄边区域（p-）的掺杂浓度相对较高 33）。 窄边区域（p-）和横向基极掺杂曲线的组合限制了基极内的耗尽区域，从而降低晶体管的穿通电压而不损失β。