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    Method and apparatus for detecting errors in data output from memory and a device failure in the memory
    3.
    发明授权
    Method and apparatus for detecting errors in data output from memory and a device failure in the memory 有权
    用于检测从存储器输出的数据中的错误和存储器中的设备故障的方法和装置

    公开(公告)号：US06519735B1

    公开(公告)日：2003-02-11

    申请号：US09217814

    申请日：1998-12-22

    Applicant: Thomas J. Holman ,  Peter D. MacWilliams

    Inventor： Thomas J. Holman ,  Peter D. MacWilliams

    IPC: G11C2900

    CPC classification number: G06F11/1028 ,  G06F11/1036

    Abstract: A method and apparatus for detecting errors in data output from memory and a device failure in the memory. In the invention, a check code is generated based on data to be input to the memory. The check code is valid when equal to zero. The check code is inverted and input along with the data as a codeword to the memory in response to a write command. The codeword is output from the memory in response to a read command. The codeword output from memory indicates whether a device in memory has failed. The inverted check code included in the codeword output from memory is re-inverted. Information indicating whether the data included in the codeword output from memory includes an error is generated based on the data and the codeword including the check code.

    Abstract translation: 一种用于检测从存储器输出的数据中的错误和存储器中的设备故障的方法和装置。 在本发明中，基于要输入到存储器的数据生成校验码。 检查码在等于零​​时有效。 响应于写命令，校验码被反转并作为代码字与数据一起输入存储器。 响应于读取命令，从存储器输出码字。 从存储器输出的码字指示存储器中的设备是否失败。 包括在从存储器输出的码字中的反转检查码被重新反转。 指示基于包括校验码的数据和码字来生成包括在存储器输出的码字中的数据是否包含错误的信息。

    Encoding scheme for failure detection in random access memories
    4.
    发明授权
    Encoding scheme for failure detection in random access memories 失效
    随机存取存储器中故障检测的编码方案

    公开(公告)号：US3963908A

    公开(公告)日：1976-06-15

    申请号：US552304

    申请日：1975-02-24

    Applicant: Santanu Das

    Inventor： Santanu Das

    IPC: G06F11/10

    CPC classification number: G06F11/1016 ,  G06F11/1036

    Abstract: A virtual encoding scheme for use in random access memories is disclosed. Data errors, incorrect memory word access errors, and errors resulting from multiple memory word access are all detectable through use of the encoding scheme. The novel approach includes the generation of two distinct check code fields which are stored along with the data. A first check code field is generated as a function of the data and is capable of reflecting all unidirectional data failures. A second check code field is generated as a function of the address of the memory word containing the data and is capable of reflecting incorrect memory word access. The two check fields can be stored either in the same physical memory location as the data or in a supplementary memory at an address numerically identical to that at which the data is kept. During readout, the two check fields are regenerated and compared to those previously stored.

    Abstract translation: 公开了一种用于随机存取存储器的虚拟编码方案。 数据错误，错误的存储器字访问错误以及由多个存储器字访问引起的错误都可以通过使用编码方案来检测。 新颖的方法包括产生与数据一起存储的两个不同的校验码字段。 根据数据生成第一个校验码字段，并能够反映所有单向数据故障。 作为包含数据的存储器字的地址的函数产生第二校验码字段，并且能够反映不正确的存储器字访问。 两个检查字段可以存储在与数据相同的物理存储器位置中，或者存储在与数据保持数据相同的地址的补充存储器中。 在读出期间，两个检查字段被重新生成并与先前存储的检查字段进行比较。

    Asymmetric soft-error resistant memory
    5.
    发明授权
    Asymmetric soft-error resistant memory 失效
    不对称软错误记忆

    公开(公告)号：US5048023A

    公开(公告)日：1991-09-10

    申请号：US311024

    申请日：1989-02-16

    Applicant: Martin G. Buehler ,  Marvin Perlman

    Inventor： Martin G. Buehler ,  Marvin Perlman

    IPC: G06F11/00 ,  G06F11/10 ,  G11C5/00 ,  H01L27/11

    CPC classification number: G06F11/1008 ,  G06F11/1076 ,  G11C5/005 ,  H01L27/11 ,  G06F11/1036

    Abstract: A memory system is provided, of the type which includes an error-correcting circuit that detects and corrects errors, which more efficiently utilizes the capacity of a memory formed of groups of binary cells whose states can be inadvertently switched by ionizing radiation. Each memory cell has an asymmetric geometry, so that ionizing radiation causes a significantly greater probability of errors in one state than in the opposite state (e.g., an erroneous switch from "1" to "0" is far more likely than a switch from "0" to "1"). An asymmetric error-correcting coding circuit can be used with the asymmetric memory cells, which requires fewer bits than an efficient symmetric error-correcting code.

    Abstract translation: 提供了一种存储系统，其类型包括检错纠错误差，其更有效地利用由状态可能被电离辐射无意中切换的二进制单元组形成的存储器的容量。 每个存储单元具有非对称几何形状，使得电离辐射在一个状态中导致比在相反状态下更大的误差概率（例如，从“1”到“0”的错误转换比从“ 0“到”1“）。 非对称误差校正编码电路可以与非对称存储器单元一起使用，这需要比有效的对称误差校正码少的位。

    Method and system for detecting a predetermined number of unidirectional errors
    6.
    发明授权
    Method and system for detecting a predetermined number of unidirectional errors 失效
    用于检测预定数量的单向误差的方法和系统

    公开(公告)号：US4691319A

    公开(公告)日：1987-09-01

    申请号：US746109

    申请日：1985-06-18

    Applicant: Bella Bose ,  Der J. Lin

    Inventor： Bella Bose ,  Der J. Lin

    IPC: G06F11/10 ,  H03M13/05 ,  H03M13/51

    CPC classification number: H03M13/51 ,  H03M13/05 ,  G06F11/1036

    Abstract: A method and system for employing systematic check codes for detecting a predetermined number of unidirectional errors in the transmission of data. In accordance with the invention check codes are produced from information codes such that for all possible pairs of (n+m)-bit data words formed by a predetermined set of n-bit information codes and corresponding m-bit check codes, either the pair of words is unordered or the Hamming distance between the data words of the pair is greater than or equal to t+1, where t is the maximum number of unidirectional errors that can be detected. First check codes are generated at a data source, second check codes are generated from the received information code at a data sink, and the received first check codes are compared with the second check codes to determine the existence of a disparity. Sequential and combinational logic circuits are provided for producing check codes having two or more bits.

    Abstract translation: 一种用于在数据传输中检测预定数量的单向错误的系统校验码的方法和系统。 根据本发明，从信息码产生检查码，使得对于由预定的一组n位信息码和相应的m位校验码形成的所有可能的（n + m）位数据字对， 的字是无序的，或者该对的数据字之间的汉明距离大于或等于t + 1，其中t是可以检测的单向错误的最大数量。 在数据源处生成第一校验码，在数据宿中从接收到的信息码生成第二校验码，并将接收到的第一校验码与第二校验码进行比较，以确定视差的存在。 提供顺序和组合逻辑电路用于产生具有两位或多位的检验码。

    Self-checking microprogram control unit with on-line error detection capability, in MOS technology
    7.
    发明公开
    Self-checking microprogram control unit with on-line error detection capability, in MOS technology 失效
    在MOS技术中自检检测微控制器具有在线错误检测能力

    公开(公告)号：EP0199120A3

    公开(公告)日：1989-03-22

    申请号：EP86104011.1

    申请日：1986-03-24

    Applicant: CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A.

    Inventor： Melgara, Marcello ,  Paolini, Maurizio ,  Turolla, Maura

    IPC: G06F11/00

    CPC classification number: G06F11/1008 ,  G06F9/226 ,  G06F11/00 ,  G06F11/0763 ,  G06F11/10 ,  G06F11/1036 ,  G06F11/1076 ,  G06F11/16 ,  G06F11/28 ,  H03M13/51

    Abstract: The control unit detects the errors concurrently with normal microinstruction execution through suitable internal checking circuits and a determined microinstruction allocation in the memory. Microinstructions comprise additional field (CS, FS) carrying the encoding, in modified Berger code, of the allocation address of the microinstruction itself and of the following one; the microinstructions of destination itself and of the following one; the microinstructions of destination of conditional jumps are allocated so that their codes are related to each other by simple logic relationships which are then reproduced by an internal circuit (CSM); the two fields, the one of the next microinstruction being duly delayed, are then compared and possible differences detect unidirectional and incorrect sequencing errors. The other errors are detected through particular implementations of some internal circuits (STK1, INC1) and duplication of others (RCT, SEL).

    Abstract translation: 控制单元通过适当的内部检查电路和存储器中确定的微指令分配来检测与正常微指令执行同时发生的错误。 微指令包括附加字段（CS，FS），其以修改的Berger代码携带微指令本身和随后的分配地址的编码; 目的地本身和以下的微指令; 分配条件跳转的目的地的微指令，使得它们的代码通过简单的逻辑关系彼此相关，然后由内部电路（CSM）再现; 然后将两个领域（下一个微指令正确延迟的）进行比较，并且可能的差异检测单向和不正确的排序错误。 通过某些内部电路（STK1，INC1）的特定实现和其他的复制（RCT，SEL）来检测其他错误。

    Self-checking memory cell array apparatus
    9.
    发明授权
    Self-checking memory cell array apparatus 失效
    自我检查记忆体阵列装置

    公开(公告)号：US5128947A

    公开(公告)日：1992-07-07

    申请号：US373963

    申请日：1989-06-30

    Applicant: Gerald Corrigan

    Inventor： Gerald Corrigan

    IPC: G06F11/10 ,  G11C29/00 ,  G11C29/38

    CPC classification number: G11C29/74 ,  G06F11/1036 ,  G11C29/38 ,  G06F11/1008 ,  G06F11/1032

    Abstract: A totally self-checking memory cell array apparatus (30) has an array (31) of memory cells (32) selectively addressed by row and column decoders (33, 35) which receive unidirectional error detecting code signals as address inputs (34, 36). Data, as a multiple bit data word (A, B, C.sub.1, C.sub.2), is stored in the array (31) in unidirectional error detecting code form. Cells in each row (1-8) of the array have two separate row select connection lines (45 and 45a) for coupling the cell to data and data complement (46, 46*) connections. Error detection circuits (44, 47) are provided which determine errors by comparing the data and data complement lines for each data bit read out of the array and for detecting when multiple bit data words read out of the array are not coded in a unidirectional error detecting code format. The above apparatus provides error indications in case of any unidirectional errors in the row or column input address signals or the row or column decoders, or any unidirectional error corruption of the data stored in the memory cell array. This is achieved without completely duplicating each memory cell in the array and all row and column decoder circuitry.

    MOS selfchecking microprogrammed control unit with on-line error detection
    10.
    发明授权
    MOS selfchecking microprogrammed control unit with on-line error detection 失效
    MOS自检微程序控制单元，具有在线错误检测功能

    公开(公告)号：US4823307A

    公开(公告)日：1989-04-18

    申请号：US839114

    申请日：1986-03-12

    Applicant: Marcello Melgara ,  Maurizio Paolini ,  Maura Torolla

    Inventor： Marcello Melgara ,  Maurizio Paolini ,  Maura Torolla

    IPC: G06F9/22 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/28 ,  H03M13/51 ,  G06F7/02 ,  G06F9/00

    CPC classification number: G06F11/1008 ,  G06F11/00 ,  G06F11/1076 ,  G06F11/28 ,  G06F9/226 ,  H03M13/51 ,  G06F11/0763 ,  G06F11/10 ,  G06F11/1036 ,  G06F11/16

    Abstract: The control unit detects the errors concurrently with normal microinstruction execution through suitable internal checking circuits and a determined microinstruction allocation in the memory. Microinstructions comprise additional fields (CS, FS) carrying the encoding, in Modified Berger code, of the allocation address of the microinstruction itself and of the following one. The microinstructions of destination of conditional jumps are allocated so that their codes are related to each other by simple logic relationships which are then reproduced by an internal circuit (CSM). The two fields, the one of the next microinstruction being duly delayed, are then compared and possible differences represent unidirectional and incorrect sequencing errors. The other errors are detected through particular implementations of some internal circuits (STK1, INC1) and duplication of others (RCT, SEL).

    Abstract translation: 控制单元通过适当的内部检查电路和存储器中确定的微指令分配来检测与正常微指令执行同时发生的错误。 微指令包括在修改的Berger代码中携带微指令本身的分配地址和随后的编码的附加字段（CS，FS）。 分配条件跳转的目的地的微指令，使得它们的代码通过简单的逻辑关系彼此相关，然后由内部电路（CSM）再现。 然后将两个领域（下一个微指令正确延迟的）进行比较，可能的差异表示单向和不正确的排序错误。 通过某些内部电路（STK1，INC1）的特定实现和其他的复制（RCT，SEL）来检测其他错误。

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