公开(公告)号：KR1020040084751A

公开(公告)日：2004-10-06

申请号：KR1020040019889

申请日：2004-03-24

Applicant: 로무 가부시키가이샤

Inventor： 사카모토타다유키

IPC: H03M1/38

CPC classification number: H03M1/14 ,  H03M1/365 ,  H03M1/38 ,  H03M1/002 ,  H03M1/1265 ,  H03M2201/528 ,  H03M2201/6107

Abstract: PURPOSE: An analog-to-digital converter suitable for preventing a malfunction and reducing power consumption is provided to prevent an operational error by modifying high-bit data. CONSTITUTION: A partial voltage generation circuit generates a plurality of partial voltages for the N bits by dividing a reference voltage. A plurality of high-bits side comparators(11-1 to 11-7) are used for comparing the input voltage with each partial voltage. Each partial voltage is in a part of the plural partial voltages, which becomes data of high bits whose bit number is more than half of the N bits. A high-bits side encoding circuit(20) encodes the comparison results from the high-order comparators and outputs the encoded comparison results as high-bit data having the bit number of the high bits. A plurality of selection circuits(16-1 to 16-3) are used for selecting a part of the partial voltages, which becomes data of low bits with a bit number being defined as half of the plurality of N bits, in accordance with the comparison results of the high-bits side comparators. A plurality of low-bits side comparators(13-1 to 13-3) are used for comparing each partial voltage of the partial voltages selected by the selection circuits with the input voltage. A low-bits side encoding circuit(30) encodes the comparison outputs from the low-bits side comparators and outputs the encoded comparison results as low-bit data having the bit number of the low bits. A logic circuit(40) outputs N bits data based on a matching being made between the high-bit data and the low-bit data. When the matching stands between the high-bit data and the low-bit data, the N bits data are outputted in accordance with predetermined conditions. When the matching does not stands therebetween, the high-bit data are modified according to the low-bit data and the N bits data are outputted in accordance with predetermined conditions.

Abstract translation: 目的：提供适合于防止故障和降低功耗的模拟 - 数字转换器，以通过修改高位数据来防止操作错误。 构成：部分电压产生电路通过划分参考电压来产生用于N位的多个局部电压。 多个高位侧比较器（11-1至11-7）用于将输入电压与每个分压进行比较。 每个分压都是多个分压的一部分，它是位数大于N位一半的高位的数据。 高位侧编码电路（20）对来自高阶比较器的比较结果进行编码，并将编码的比较结果输出为具有高位位数的高位数据。 多个选择电路（16-1至16-3）用于选择部分电压的一部分，这是根据该多个选择电路中的一部分被定义为多个N位的一半的低位数据 高比特比较器的比较结果。 多个低位侧比较器（13-1至13-3）用于将由选择电路选择的部分电压的每个部分电压与输入电压进行比较。 低位侧编码电路（30）对来自低位侧比较器的比较输出进行编码，并输出编码比较结果作为具有低位位数的低位数据。 逻辑电路（40）基于在高位数据和低位数据之间的匹配来输出N位数据。 当匹配站在高位数据和低位数据之间时，根据预定条件输出N位数据。 当匹配不在其间时，根据低位数据修改高位数据，并根据预定条件输出N位数据。