公开(公告)号：EP0240286A3

公开(公告)日：1988-10-26

申请号：EP87302735

申请日：1987-03-30

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Watanabe, Koji ,  Hayashi, Katsuhiko Mingle AP Akane Ichibankan 2B ,  Minakuchi, Nobuaki ,  Misaki, Masayuki ,  Terai, Kenichi ,  Nakama, Yasutoshi

IPC: H03G05/16 ,  G11B05/035 ,  H04R25/00

CPC classification number: H03G5/16 ,  G11B5/035

Abstract: Low-frequency components (S2) are selected from the outputted analog sound signal (S1) so that a low-pitched sound signal is derived from the analog sound signal. A key of the low-pitched sound signal is lowered so that a very-low-pitched sound signal (S3) is derived from the low-pitched sound signal (S2). The analog sound signal (S1) and the very-low-pitched sound signal (S3) may be converted into corresponding sounds respectively (S4).

公开(公告)号：EP0228534A3

公开(公告)日：1988-03-02

申请号：EP86115264

申请日：1986-11-04

Applicant: International Business Machines Corporation

Inventor： Dost, Martin Hans-Ulrich ,  Hopner, Emil ,  Melas, Constantin Michael ,  Provazek, Lionel Daniel

IPC: G11B20/10 ,  G11B05/035

CPC classification number: G11B20/10046 ,  G11B5/035 ,  G11B20/10009

Abstract: A pulse signal conditioner filters and equalizes signal pulses representing digital data whether or not obtained from a magnetic recording device. Modified low pass filters filter (23, 25) the pulse signals and also derive and feed forward the second time derivative of the filtered pulse signals. The filtered pulse and the second time (234, 254) derivative thereof are combined to (230, 250) slim the pulse. Further slimming is provided by delay line equalizers (27, 29) having three paths. A first path (271) for attenuating the pulse signals, a second path (272) for delaying the pulse signals for a first delay, and a third path (273-274) for delaying the pulse signals for a second delay and attenuation. Pulse signals from the three paths are combined (270) to further slim the pulse.

公开(公告)号：EP0154086A3

公开(公告)日：1987-09-30

申请号：EP84308293

申请日：1984-11-29

Applicant: MAGNETIC PERIPHERALS INC.

Inventor： Vinding, Jorgen Plesner

IPC: G11B20/14 ,  H04L25/49 ,  H03M05/14 ,  G11B20/10 ,  G11B05/035

CPC classification number: G11B20/1426 ,  G11B5/035 ,  G11B20/10009

Abstract: @ A data recovery circuit for a data recording/transmission system wherein information is encoded in an equalised data signal comprising at least partly doublet pulses, each valid doublet pulse comprising two adjacent opposite polarity pulses, the data recovery circuit being arranged to distinguish individual doublets from noise in the equalised data signal, receiving the equalised data signal, and responsive thereto supplying a doublet indentification signal identifying individual portions of the equalised data signal as constituting doublets, comprises a differentiator (11) connected to receive the equalised data signal to provide an output signal having a waveform following the time derivative of the equalised data signal, and having a predetermined delay time. A first comparator (15, 16) is connected to receive an output of the differentiator (11) for providing, as an output, a logic level signal having first, second and third instantaneous states indicating that the output signal of the differentiator is respectively less than, within, or greater than a first predetermined signal range whose minimum corresponds to an equalised data signal slope smaller than a first predetermined negative slope, and whose maximum corresponds to a slope greater than a second predetermined positive slope. An amplifier (20) is connected to receive a delayed equalised data signal for supplying an amplified output signal having a waveform following the equalised data signal and delayed by a predetermined delay time therefrom. A delay element is connected to receive the equalised data signal, for supplying the delayed equalised data signal to the amplifier (20). An analog gate (23, 24) is connected to receive the amplified output signal from the amplifier and the logic level signal from the first comparator (15) for supplying an output signal including a first portion following the amplified output signal while the logic level of the first comparator means has exclusively its first state and a second portion following the amplified output signal while the logic level signal of the first comparator has exclusively its third state, each portion having a predetermined level otherwise. A second comparator (27) is connected to receive the output of signal of the analog gate (23, 24) for producing responsive thereto, a logic signal having first, second and third instantaneous states, the first state and the third state of the second comparator indicating, respectively, that the first portion and the second portion of the output signal of the analog gate are outside a second predetermined signal range, and the second state of the second comparator indicating that, both first and second portions of the output signal of the analog gate are within the second predetermined range, the second predetermined signal range substantially corresponding to the minimum excursion of the equalised data signal between points (i) having slopes corresponding to the first and second predetermined slopes and (ii) between peaks of a valid doublet pulse, the second comparator producing a doublet identification signal.

公开(公告)号：WO1996037882A1

公开(公告)日：1996-11-28

申请号：PCT/US1996007710

申请日：1996-05-23

Applicant: MAXTOR CORPORATION

Inventor： MAXTOR CORPORATION ,  MATHEWS, Harlan ,  MCNEIL, Michael ,  BAILEY, Roger, G.

IPC: G11B05/035

CPC classification number: G11B20/10027 ,  G11B5/012 ,  G11B5/02 ,  G11B5/027 ,  G11B5/035 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/10203 ,  G11B20/10314 ,  G11B2005/001 ,  G11B2005/0016

Abstract: The present invention relates to circuitry for processing an analog read signal, such as a signal produced by a magnetoresistive head (18), in a magnetic data storage system. The circuitry processes an analog read signal before the signal reaches an analog to digital converter (54). In one embodiment, the invention comprises circuitry (44) for equalizing the amplitudes of the positive and negative pulses in the analog read signal. In another embodiment, the invention comprises circuitry (42) for reducing the baseline shift of the analog read signal. The invention may be used in magnetic data storage systems using any conventional data detection method.

Abstract translation: 本发明涉及用于在磁数据存储系统中处理诸如由磁阻头（18）产生的信号的模拟读信号的电路。 在信号到达模数转换器（54）之前，电路处理模拟读取信号。 在一个实施例中，本发明包括用于均衡模拟读取信号中的正和负脉冲的振幅的电路（44）。 在另一个实施例中，本发明包括用于减小模拟读取信号的基线偏移的电路（42）。 本发明可以用于使用任何常规数据检测方法的磁数据存储系统。