公开(公告)号：US08333323B2

公开(公告)日：2012-12-18

申请号：US12819671

申请日：2010-06-21

Applicant: Neil Richardson ,  James Timothy Sauerwein, Jr. ,  Douglas Hinson ,  Ynjiun Paul Wang

Inventor： Neil Richardson ,  James Timothy Sauerwein, Jr. ,  Douglas Hinson ,  Ynjiun Paul Wang

IPC: G06K7/00

CPC classification number: G06K7/0008 ,  Y10T307/696

Abstract: A mobile device comprising: a data collection device; a trigger to activate the data collection device; a communication system for wireless communications; a display for displaying information; a processor for controlling software and firmware operation; a keypad for entering data for the processor; a power supply for providing power to the mobile device, the power supply comprising a fuel cell or an ultracapacitor; and a housing for supporting the data collection device, trigger, communication system, display, processor, keypad and power supply.

Abstract translation: 一种移动设备，包括：数据收集设备; 激活数据采集设备的触发器; 一种用于无线通信的通信系统; 用于显示信息的显示器; 用于控制软件和固件操作的处理器; 用于输入处理器的数据的键盘; 用于向移动设备提供电力的电源，所述电源包括燃料电池或超级电容器; 以及用于支持数据采集装置，触发器，通信系统，显示器，处理器，键盘和电源的外壳。

公开(公告)号：US06636064B1

公开(公告)日：2003-10-21

申请号：US09648092

申请日：2000-08-25

Applicant: Akella V. S. Satya ,  David L. Adler ,  Neil Richardson ,  Kurt H. Weiner ,  David J. Walker

Inventor： Akella V. S. Satya ,  David L. Adler ,  Neil Richardson ,  Kurt H. Weiner ,  David J. Walker

IPC: G01R3128

CPC classification number: H01L22/34 ,  G01N21/66 ,  G01N21/9501 ,  G01N21/956 ,  G01R31/2884 ,  G01R31/307 ,  H01J2237/2817

Abstract: Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scanning area is disclosed. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The die includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The first plurality of test structures or the second plurality of test structures has a probe pad coupled to at least one test structure.

Abstract translation: 公开了具有上层和下层的半导体管芯。 模具包括形成在半导体管芯的下金属层中的下部测试结构。 下导电测试结构具有第一端和第二端，其中第一端耦合到预定的电压电平。 模具还具有形成在下金属层上的绝缘层和形成在半导体管芯的上金属层中的上测试结构。 上导电测试结构与下导电测试结构的第二端耦合，并且上金属层形成在绝缘层上。 芯片还包括与上测试结构耦合的至少一个探针焊盘。 优选地，下测试结构的第一端耦合到标称接地电位。 在另一实施方案中，上测试结构是电压对比元件。 在另一实施例中，公开了具有扫描区域的半导体管芯。 半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。 模具包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分地位于扫描区域内。 第一多个测试结构或第二多个测试结构具有耦合到至少一个测试结构的探针焊盘。

公开(公告)号：US06445199B1

公开(公告)日：2002-09-03

申请号：US09648379

申请日：2000-08-25

Applicant: Akella V. S. Satya ,  Brian C. Leslie ,  Gustavo A. Pinto ,  Robert Thomas Long ,  Neil Richardson ,  Bin-Ming Benjamin Tsai

Inventor： Akella V. S. Satya ,  Brian C. Leslie ,  Gustavo A. Pinto ,  Robert Thomas Long ,  Neil Richardson ,  Bin-Ming Benjamin Tsai

IPC: G01R31308

CPC classification number: H01L22/34 ,  G01N21/66 ,  G01N21/956 ,  G01R31/2884 ,  G01R31/307 ,  H01J2237/2817

Abstract: Disclosed is a method of inspecting a sample. The sample is illuminated with an incident beam, thereby causing voltage contrast within structures present on the sample. Voltage contrast is detected within the structures. Information from the detected voltage contrast is stored, and position data concerning the location of features corresponding to at least a portion of the stored voltage contrast information is also stored. In a specific embodiment, the features represent electrical defects present on the sample. In another embodiment, the stored position data is in the form of a two dimensional map. In another aspect, the sample is re-inspected and the stored position data is used in analyzing data resulting from the re-inspection.

Abstract translation: 公开了一种检查样品的方法。 样品用入射光照射，从而在样品中存在的结构内引起电压对比。 在结构内检测到电压对比度。 存储来自检测到的电压对比度的信息，并且还存储与存储的电压对比度信息的至少一部分相对应的特征位置的位置数据。 在具体实施例中，特征表示样品上存在的电缺陷。 在另一个实施例中，存储的位置数据是二维地图的形式。 在另一方面，重新检查样本，并且将存储的位置数据用于分析由重新检查产生的数据。

公开(公告)号：US5608037A

公开(公告)日：1997-03-04

申请号：US443847

申请日：1995-05-18

Applicant: Ellis Reinherz ,  Peter Sayre ,  Hsiu-Ching Chang ,  Neil Richardson

Inventor： Ellis Reinherz ,  Peter Sayre ,  Hsiu-Ching Chang ,  Neil Richardson

IPC: A61K38/00 ,  C07K14/705 ,  C07K16/28 ,  C12N15/00 ,  C07K14/00

CPC classification number: C07K16/2806 ,  C07K14/70507 ,  A61K38/00

Abstract: A cDNA sequence encoding human T11 or a fragment thereof which is capable of inhibiting T-lymphocyte activation.

Abstract translation: 编码能够抑制T淋巴细胞活化的人T11或其片段的cDNA序列。

公开(公告)号：US5140164A

公开(公告)日：1992-08-18

申请号：US640636

申请日：1991-01-14

Applicant: Christopher G. Talbot ,  Neil Richardson ,  Douglas Masnaghetti

Inventor： Christopher G. Talbot ,  Neil Richardson ,  Douglas Masnaghetti

IPC: H01J37/04 ,  G01Q60/00 ,  G01R31/307 ,  H01J37/30 ,  H01J37/305 ,  H01L21/66 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04

CPC classification number: B24B37/013 ,  H01J37/3005 ,  H01J37/3056 ,  H01L21/76892 ,  H01L22/26 ,  G01R31/307

Abstract: Apparatus is provided which includes a FIB column having a vacuum chamber for receiving an IC, means for applying a FIB to the IC, means for detecting secondary charged particles emitted as the FIB is applied to the IC, and means for electrically stimulating the IC as the FIB is applied to the IC. The apparatus may be used, for example, (1) to locate a conductor buried under dielectric material within the IC, (2) for determining milling end-point when using the FIB to expose a buried conductor of the IC, and (3) to verify the repair of an IC step-by-step as the repair is made.

公开(公告)号：US20120281275A1

公开(公告)日：2012-11-08

申请号：US13552642

申请日：2012-07-19

Applicant: Ady Levy ,  Samuel Ngai ,  Christopher F. Bevis ,  Stefano Concina ,  John Fielden ,  Walter Mieher ,  Dieter Mueller ,  Neil Richardson ,  Dan Wack ,  Larry Wagner

Inventor： Ady Levy ,  Samuel Ngai ,  Christopher F. Bevis ,  Stefano Concina ,  John Fielden ,  Walter Mieher ,  Dieter Mueller ,  Neil Richardson ,  Dan Wack ,  Larry Wagner

IPC: G06K7/10 ,  B05C11/00 ,  B05C9/00 ,  B05C11/02 ,  B05C5/02 ,  C23C16/44

CPC classification number: G01N21/9505 ,  G01N21/3581 ,  H01L22/12

Abstract: Systems and methods for determining one or more characteristics of a specimen using radiation in the terahertz range are provided. One system includes an illumination subsystem configured to illuminate the specimen with radiation. The system also includes a detection subsystem configured to detect radiation propagating from the specimen in response to illumination of the specimen and to generate output responsive to the detected radiation. The detected radiation includes radiation in the terahertz range. In addition, the system includes a processor configured to determine the one or more characteristics of the specimen using the output.

Abstract translation: 提供了使用太赫兹范围内的辐射来确定样本的一个或多个特征的系统和方法。 一个系统包括被配置为用辐射照射样本的照明子系统。 该系统还包括检测子系统，该检测子系统被配置为响应于样本的照射来检测从样本传播的辐射，并响应于检测到的辐射产生输出。 检测到的辐射包括太赫兹范围内的辐射。 另外，该系统包括配置成使用该输出来确定样本的一个或多个特性的处理器。

公开(公告)号：US20080246030A1

公开(公告)日：2008-10-09

申请号：US11675021

申请日：2007-02-14

Applicant: Akella V.S. Satya ,  Gustavo A. Pinto ,  David L. Adler ,  Robert Thomas Long ,  Neil Richardson ,  Kurt H. Weiner ,  David J. Walker ,  Lynda C. Mantalas ,  Padma A. Satya

Inventor： Akella V.S. Satya ,  Gustavo A. Pinto ,  David L. Adler ,  Robert Thomas Long ,  Neil Richardson ,  Kurt H. Weiner ,  David J. Walker ,  Lynda C. Mantalas ,  Padma A. Satya

IPC: H01L23/58 ,  H01L21/00

CPC classification number: H01L23/5226 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Abstract translation: 公开了具有扫描区域的半导体管芯。 半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。 半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。 测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

公开(公告)号：US20070145266A1

公开(公告)日：2007-06-28

申请号：US11450757

申请日：2006-06-09

Applicant: Avi Cohen ,  David Adler ,  Neil Richardson

Inventor： Avi Cohen ,  David Adler ,  Neil Richardson

IPC: G21K7/00

CPC classification number: H01J37/28 ,  H01J37/04 ,  H01J37/06 ,  H01J2237/04924 ,  H01J2237/06316 ,  H01J2237/162 ,  H01J2237/2817

Abstract: One embodiment relates to an apparatus which utilizes an electron beam for inspection or metrology of a substrate. The apparatus includes a CRT-type gun and deflectors to generate and scan the electron beam. The CRT-type gun may optionally be in a sealed vacuum. Another embodiment relates to a method of inspecting a substrate or measuring an aspect of the substrate. The method includes focusing an electron beam using electrostatic lenses formed by metal plates supported by and separated by fused glass beads or other insulating material. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及利用电子束来检查或测量基底的装置。 该装置包括CRT型枪和用于产生和扫描电子束的偏转器。 CRT型枪可以可选地处于密封真空中。 另一实施例涉及一种检查衬底或测量衬底的方面的方法。 该方法包括使用由熔融玻璃珠或其它绝缘材料支撑和分离的金属板形成的静电透镜来聚焦电子束。 还公开了其它实施例和特征。

公开(公告)号：US06528818B1

公开(公告)日：2003-03-04

申请号：US09648380

申请日：2000-08-25

Applicant: Akella V. S. Satya ,  Gustavo A. Pinto ,  David L. Adler ,  Robert Thomas Long ,  Neil Richardson ,  Kurt H. Weiner ,  David J. Walker ,  Lynda C. Mantalas

Inventor： Akella V. S. Satya ,  Gustavo A. Pinto ,  David L. Adler ,  Robert Thomas Long ,  Neil Richardson ,  Kurt H. Weiner ,  David J. Walker ,  Lynda C. Mantalas

IPC: H01L2358

CPC classification number: H01L22/34 ,  G01N21/66 ,  G01N21/956 ,  G01R31/2884 ,  G01R31/307 ,  H01J2237/2817

Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Abstract translation: 公开了具有扫描区域的半导体管芯。 半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。 半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。 测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

公开(公告)号：US06509197B1

公开(公告)日：2003-01-21

申请号：US09648212

申请日：2000-08-25

Applicant: Akella V. S. Satya ,  Robert Thomas Long ,  Lynda C. Mantalas ,  Gustavo A. Pinto ,  Neil Richardson

Inventor： Akella V. S. Satya ,  Robert Thomas Long ,  Lynda C. Mantalas ,  Gustavo A. Pinto ,  Neil Richardson

IPC: H01L2100

CPC classification number: H01L22/34 ,  G01N21/66 ,  G01N21/956 ,  G01R31/2884 ,  G01R31/307 ,  H01J2237/2817 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.