公开(公告)号：US20200035560A1

公开(公告)日：2020-01-30

申请号：US16316330

申请日：2017-08-25

Applicant: Intel Corporation

Inventor： Bruce BLOCK ,  Valluri R. RAO ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Doug INGERLY ,  Kimin JUN ,  Kevin O'BRIEN ,  Patrick MORROW ,  Szyua S. LIAO

IPC: H01L21/822 ,  H01L29/04 ,  H01L29/08 ,  H01L23/528 ,  H01L23/00 ,  H01L29/16 ,  H01L29/20 ,  H01L27/092 ,  H01L27/12 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/683 ,  H01L29/06 ,  H01L21/66

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

公开(公告)号：US20190280188A1

公开(公告)日：2019-09-12

申请号：US16348364

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Justin BROCKMAN ,  Christopher WIEGAND ,  MD Tofizur RAHMAN ,  Daniel OUELETTE ,  Angeline SMITH ,  Juan ALZATE VINASCO ,  Charles KUO ,  Mark DOCZY ,  Kaan OGUZ ,  Kevin O'BRIEN ,  Brian DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/12 ,  H01F41/30

Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.

公开(公告)号：US20200211974A1

公开(公告)日：2020-07-02

申请号：US16232524

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Kevin LIN ,  Kevin O'BRIEN ,  Hui Jae YOO

IPC: H01L23/532 ,  H01L43/10 ,  H01L43/12 ,  H01L21/768 ,  H01L23/522

Abstract: A multilayer conductive line is disclosed. The multilayer conductive line includes a dielectric layer, a Ta barrier layer on the dielectric layer and a superlattice on the Ta barrier layer. The superlattice includes a plurality of interleaved ferromagnetic and non-ferromagnetic material.

公开(公告)号：US20200006427A1

公开(公告)日：2020-01-02

申请号：US16024684

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Kevin O'BRIEN ,  Eungnak HAN ,  Manish CHANDHOK ,  Gurpreet SINGH ,  Nafees KABIR ,  Kevin LIN ,  Rami HOURANI ,  Abhishek SHARMA ,  Hui Jae YOO

IPC: H01L27/24 ,  H01L45/00

Abstract: An integrated circuit structure includes a first material block comprising a first block insulator layer and a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers. A second material block is stacked on the first material block and comprises a second block insulator layer, and a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers. At least one pillar extends through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks.

公开(公告)号：US20200006637A1

公开(公告)日：2020-01-02

申请号：US16024714

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Kaan OGUZ ,  Christopher WIEGAND ,  Angeline SMITH ,  Noriyuki SATO ,  Kevin O'BRIEN ,  Benjamin BUFORD ,  Ian YOUNG ,  MD Tofizur RAHMAN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.

公开(公告)号：US20240194533A1

公开(公告)日：2024-06-13

申请号：US18389625

申请日：2023-12-19

Applicant: Intel Corporation

Inventor： Valluri R. RAO ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Doug INGERLY ,  Kimin JUN ,  Kevin O'BRIEN ,  Paul FISCHER ,  Szuya S. LIAO ,  Bruce BLOCK

IPC: H01L21/822 ,  G01R1/073 ,  H01L21/306 ,  H01L21/66 ,  H01L21/683 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L21/8221 ,  H01L21/30625 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L22/14 ,  H01L23/528 ,  H01L23/53233 ,  H01L24/03 ,  H01L24/05 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  G01R1/07307 ,  H01L24/08 ,  H01L25/0657 ,  H01L27/1214 ,  H01L27/1222 ,  H01L29/66545 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/08147 ,  H01L2225/06565

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

公开(公告)号：US20210175124A1

公开(公告)日：2021-06-10

申请号：US17112697

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Valluri R. RAO ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Doug INGERLY ,  Kimin JUN ,  Kevin O'BRIEN ,  Paul FISCHER ,  Szuya S. LIAO ,  Bruce BLOCK

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/683 ,  H01L23/00 ,  H01L27/092 ,  H01L21/306 ,  H01L29/04 ,  H01L23/528 ,  H01L29/08 ,  H01L21/66 ,  H01L29/06 ,  H01L29/20 ,  H01L23/532 ,  H01L29/16 ,  G01R1/073 ,  H01L29/66 ,  H01L25/065

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.