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1.发明授权公开(公告)号：US06192082B1
公开(公告)日：2001-02-20
申请号：US09191917
申请日：1998-11-13
Applicant: Michael P. Moriarty , Thanh T. Tran
Inventor： Michael P. Moriarty , Thanh T. Tran
IPC: H04B166
CPC classification number: H04N21/4143 , H04N5/4401 , H04N21/440218
Abstract: A digital television (DTV) data format converter of a system automatically detects whether a serial data stream includes parity data and converts the serial DTV data stream to a parallel DTV data stream. The DTV data format converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a first conversion protocol if the serial DTV data stream includes parity data. If the serial DTV data stream does not include parity data, the converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a second conversion protocol. In this way, the converter accommodates a serial DTV data stream with or without parity data. The DTV data format converter may be implemented in the form of a peripheral component interconnect (PCI) card, permitting compatibility with computer systems and other PCI-based systems. The DTV data format converter may include a receiver block, a transmitter block, and a buffer.
Abstract translation: 系统的数字电视（DTV）数据格式转换器自动检测串行数据流是否包括奇偶校验数据，并将串行DTV数据流转换为并行DTV数据流。 如果串行DTV数据流包括奇偶校验数据，则DTV数据格式转换器根据第一转换协议发送从串行DTV数据流转换的并行DTV数据流。 如果串行DTV数据流不包括奇偶校验数据，则转换器根据第二转换协议发送从串行DTV数据流转换的并行DTV数据流。 以这种方式，转换器容纳具有或不具有奇偶校验数据的串行DTV数据流。 DTV数据格式转换器可以以周边组件互连（PCI）卡的形式实现，允许与计算机系统和其他基于PCI的系统的兼容性。 DTV数据格式转换器可以包括接收器块，发送器块和缓冲器。
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公开(公告)号：US5963652A
公开(公告)日：1999-10-05
申请号：US667582
申请日：1996-07-12
Applicant: Thanh T. Tran , Gokalp Bayramoglu , William H. Nott , Hiten N. Dalal , Conrad M. Allen, Jr.
Inventor： Thanh T. Tran , Gokalp Bayramoglu , William H. Nott , Hiten N. Dalal , Conrad M. Allen, Jr.
CPC classification number: H03G1/02
Abstract: A computer system has a speaker, a unit having a central processor, a monitor separate from the unit, a video cable connecting the unit to the monitor, and a volume control for the speaker, the volume control being mounted in the monitor. Circuitry in the unit responds to the volume control by adjusting the volume output of the speaker.
Abstract translation: 计算机系统具有扬声器，具有中央处理器的单元，与该单元分离的监视器，将该单元连接到监视器的视频电缆以及扬声器的音量控制，音量控制装置安装在监视器中。 本机中的电路通过调节扬声器的音量输出来响应音量控制。
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公开(公告)号：US5281861A
公开(公告)日：1994-01-25
申请号：US855453
申请日：1992-03-19
Applicant: Thanh T. Tran , Clarence Y. Mar , Javier F. Izquierdo
Inventor： Thanh T. Tran , Clarence Y. Mar , Javier F. Izquierdo
CPC classification number: G06F1/10 , H03K19/01806
Abstract: A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.
Abstract translation: 时钟信号分布在电路板上，并以连接器的形式分布在正弦波上。 位于时钟电路附近的电路将正弦波转换成相同的频率方波，供时钟电路使用。 转换器电路的输出级提供高输出电平来驱动CMOS电路。 输出晶体管被上拉至5伏特，但是先前的晶体管被上拉至6.3伏，从而补偿基极到发射极的下降。
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公开(公告)号：US08380053B2
公开(公告)日：2013-02-19
申请号：US12330338
申请日：2008-12-08
Applicant: Thanh T. Tran , Todd C. Hiers , Ivan Garcia , Jian Wang
Inventor： Thanh T. Tran , Todd C. Hiers , Ivan Garcia , Jian Wang
IPC: H04N5/917
CPC classification number: G09G5/363 , G09G2320/0252 , G09G2360/06 , G09G2360/121 , G09G2360/18 , H04N19/436 , H04N19/61
Abstract: A system and method for allocating video processing tasks over multiple video processors include an apparatus. The apparatus includes a plurality of video processors. Each video processor includes a first processor that processes video data and manages buffers used in conversion and displaying video data. The video processor includes a second processor that performs video data signal processing and manages buffers used in processing video data. The apparatus also includes a switch coupled to each video processor, as well as video inputs and video outputs. A third processor coupled to the switch, and a memory coupled to each video processor and to the third processor, are also part of the apparatus. The switch selectively couples a video processor to a video input or a video output, the third processor configures the switch based on processing requirements of each video stream, and the memory buffers and stores video data.
Abstract translation: 用于在多个视频处理器上分配视频处理任务的系统和方法包括一种装置。 该装置包括多个视频处理器。 每个视频处理器包括处理视频数据并管理用于转换和显示视频数据的缓冲器的第一处理器。 视频处理器包括执行视频数据信号处理并管理在处理视频数据中使用的缓冲器的第二处理器。 该装置还包括耦合到每个视频处理器的开关，以及视频输入和视频输出。 耦合到开关的第三处理器和耦合到每个视频处理器和第三处理器的存储器也是该装置的一部分。 开关将视频处理器选择性地耦合到视频输入或视频输出，第三处理器基于每个视频流的处理要求配置开关，并且存储器缓冲并存储视频数据。
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公开(公告)号：US07305020B2
公开(公告)日：2007-12-04
申请号：US10357255
申请日：2003-02-03
Applicant: Thanh T. Tran , Ce Liu , Kenneth W. Egan
Inventor： Thanh T. Tran , Ce Liu , Kenneth W. Egan
IPC: H04B1/69
Abstract: A method and system is disclosed for spreading the power associated with digital signals being transmitted to lower electromagnetic interference (EMI) emissions. After being transmitted across a transmission line, a representation of the original digital signal is recovered and provided to a destination device.
Abstract translation: 公开了一种方法和系统，用于将与传输的数字信号相关联的功率扩展到较低的电磁干扰（EMI）发射。 在通过传输线传输之后，原始数字信号的表示被恢复并提供给目的设备。
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Patent Agency Ranking
公开(公告)号：US06501836B1
公开(公告)日：2002-12-31
申请号：US08450388
申请日：1995-05-25
Applicant: Thanh T. Tran , Kurtis J. Bowman
Inventor： Thanh T. Tran , Kurtis J. Bowman
IPC: H04M1100
CPC classification number: G06F3/16 , H04M1/6033 , H04M1/62 , H04R5/02 , H04R2499/15
Abstract: An audio system for multimedia computer systems and method for use are provided including an audio module having speakers, a microphone and associated circuitry. The audio module is adapted to be interposed between a monitor and a monitor pedestal such that the audio module swivels and tilts in concert with the monitor. The circuitry is adapted to drive the audio module speakers and to drive only one speaker and the microphone in a speaker phone mode.
Abstract translation: 提供了一种用于多媒体计算机系统和使用方法的音频系统，包括具有扬声器，麦克风和相关电路的音频模块。 音频模块适于插入监视器和监视器基座之间，使得音频模块与显示器一起旋转并倾斜。 电路适用于驱动音频模块扬声器，并在扬声器电话模式下仅驱动一个扬声器和麦克风。
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公开(公告)号：US20100142931A1
公开(公告)日：2010-06-10
申请号：US12330338
申请日：2008-12-08
Applicant: Thanh T. Tran , Todd C. Hiers , Ivan Garcia , Jian Wang
Inventor： Thanh T. Tran , Todd C. Hiers , Ivan Garcia , Jian Wang
CPC classification number: G09G5/363 , G09G2320/0252 , G09G2360/06 , G09G2360/121 , G09G2360/18 , H04N19/436 , H04N19/61
Abstract: A system and method for allocating video processing tasks over multiple video processors include an apparatus. The apparatus includes a plurality of video processors. Each video processor includes a first processor that processes video data and manages buffers used in conversion and displaying video data. The video processor includes a second processor that performs video data signal processing and manages buffers used in processing video data. The apparatus also includes a switch coupled to each video processor, as well as video inputs and video outputs. A third processor coupled to the switch, and a memory coupled to each video processor and to the third processor, are also part of the apparatus. The switch selectively couples a video processor to a video input or a video output, the third processor configures the switch based on processing requirements of each video stream, and the memory buffers and stores video data.
Abstract translation: 用于在多个视频处理器上分配视频处理任务的系统和方法包括一种装置。 该装置包括多个视频处理器。 每个视频处理器包括处理视频数据并管理用于转换和显示视频数据的缓冲器的第一处理器。 视频处理器包括执行视频数据信号处理并管理在处理视频数据中使用的缓冲器的第二处理器。 该装置还包括耦合到每个视频处理器的开关，以及视频输入和视频输出。 耦合到开关的第三处理器和耦合到每个视频处理器和第三处理器的存储器也是该装置的一部分。 开关将视频处理器选择性地耦合到视频输入或视频输出，第三处理器基于每个视频流的处理要求配置开关，并且存储器缓冲并存储视频数据。
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8.发明授权Non-uniform decoupling capacitor distribution for providing more uniform noise reduction across chip 有权非均匀去耦电容分布，可在芯片上提供更均匀的降噪公开(公告)号：US07080337B2
公开(公告)日：2006-07-18
申请号：US10749501
申请日：2003-12-31
Applicant: Thanh T. Tran
Inventor： Thanh T. Tran
IPC: G06F17/50
CPC classification number: G06F17/5036 , H01L2224/16227 , H01L2924/15313 , H01L2924/19015 , H01L2924/19041 , H01L2924/19104 , H01L2924/19105 , H01L2924/19106 , H05K1/0231 , H05K1/185 , H05K2201/10545 , H05K2201/10734 , H05K2203/1572
Abstract: An embodiment of the present invention includes a method of providing a non-uniform distribution of decoupling capacitors to provide a more uniform noise level across the chip. Leads on a packaged semiconductor chip are grouped into two or more regions. Types of leads needing decoupling capacitors are grouped into lead categories. For each region, there may be one or more lead categories therein. One or more decoupling capacitors are preferably assigned to each lead category in each region. Calculations may be performed to estimate a desired capacitance for each decoupling capacitor for each lead category in each region. When a chip has different components operating at different switching frequencies, different voltages, and/or different switching currents, the distribution of the decoupling capacitors will likely be non-uniform to provide a more uniform noise level across the chip, as compared to a uniform distribution of decoupling capacitors for the chip.
Abstract translation: 本发明的实施例包括提供去耦电容器的不均匀分布以在芯片上提供更均匀的噪声电平的方法。 封装的半导体芯片上的引线被分组为两个或更多个区域。 需要去耦电容器的引线类型分为引线类别。 对于每个区域，其中可以有一个或多个引线类别。 一个或多个去耦电容器优选地分配给每个区域中的每个引线类别。 可以执行计算，以估计每个区域中每个引线类别的每个去耦电容器的期望电容。 当芯片具有以不同开关频率，不同电压和/或不同开关电流工作的不同部件时，去耦电容器的分布可能不均匀，以便在整个芯片上提供更均匀的噪声电平，与均匀 芯片去耦电容的分布。
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公开(公告)号：US5157277A
公开(公告)日：1992-10-20
申请号：US635721
申请日：1990-12-28
Applicant: Thanh T. Tran , David G. Abdoo
Inventor： Thanh T. Tran , David G. Abdoo
CPC classification number: H03K5/15026 , G06F1/10
Abstract: A clock buffer circuit for a computer system, and a computer system incorporating the same, are disclosed. The clock buffer circuit includes a differential input buffer for receiving the input clock signal, with its output coupled to the input of a phase locked loop (PLL). The switching level of the differential input buffer is adjustable, either by adjusting the DC bias applied to the input clock signal, or by adjusting the reference signal, which changes the point in the cycle of the input clock signal at which the differential buffer switches. The PLL synchronizes its output to an edge of the output of the differential buffer, but maintains the same duty cycle (e.g., 50%). Accordingly, the clock buffer circuit may have its delay adjusted, by modifying a voltage divider, applying a variable voltage, or programmably via a digital-to-analog converter, to match the delays of other clock buffer circuits in the computer system, reducing the clock skew in the system. A sine wave may be used as the input clock signal, so that harmonic noise is reduced in the system.
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公开(公告)号：US06359987B1
公开(公告)日：2002-03-19
申请号：US08857258
申请日：1997-05-16
Applicant: Thanh T. Tran , Hiten N. Dalal , Kurtis J. Bowman
Inventor： Thanh T. Tran , Hiten N. Dalal , Kurtis J. Bowman
IPC: H04R2900
CPC classification number: H04R29/001 , H04R5/02 , H04S7/308
Abstract: A computer system having automatic speaker detection circuitry is disclosed. The typical computer system includes a central processing unit, a data input device, and a sound card. Further, there is an audio amplifier, as well as an automatic detection and selection circuit that may be within the sound card or the audio amplifier or just part of the computer system as a whole. This automatic detection selection device is able to determine an impedance load of an output device attached to the computer system, namely, a speaker system, and is able to disable the audio amplifier within the computer system upon determining the impedance load and matching that impedance load against a selected value indicating that no amplification of the signal is required for the output device. Further, an audio sound equalizer is part of the system and can be bypassed in the same manner that the audio amplifier is, namely, that particular impedance load is measured indicating that no equalization is necessary.
Abstract translation: 公开了一种具有自动扬声器检测电路的计算机系统。 典型的计算机系统包括中央处理单元，数据输入设备和声卡。 此外，还有一个音频放大器，以及一个自动检测和选择电路，它可能在声卡或音频放大器内，或者只是整个计算机系统的一部分。 该自动检测选择装置能够确定附接到计算机系统（即扬声器系统）的输出装置的阻抗负载，并且能够在确定阻抗负载并匹配该阻抗负载之后禁用计算机系统内的音频放大器 对应于选择的值，指示输出设备不需要放大信号。 此外，音频声音均衡器是系统的一部分，并且可以以与音频放大器相同的方式旁路，即，测量到指示不需要均衡的特定阻抗负载。
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