公开(公告)号：US06192082B1

公开(公告)日：2001-02-20

申请号：US09191917

申请日：1998-11-13

Applicant: Michael P. Moriarty ,  Thanh T. Tran

Inventor： Michael P. Moriarty ,  Thanh T. Tran

IPC: H04B166

CPC classification number: H04N21/4143 ,  H04N5/4401 ,  H04N21/440218

Abstract: A digital television (DTV) data format converter of a system automatically detects whether a serial data stream includes parity data and converts the serial DTV data stream to a parallel DTV data stream. The DTV data format converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a first conversion protocol if the serial DTV data stream includes parity data. If the serial DTV data stream does not include parity data, the converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a second conversion protocol. In this way, the converter accommodates a serial DTV data stream with or without parity data. The DTV data format converter may be implemented in the form of a peripheral component interconnect (PCI) card, permitting compatibility with computer systems and other PCI-based systems. The DTV data format converter may include a receiver block, a transmitter block, and a buffer.

Abstract translation: 系统的数字电视（DTV）数据格式转换器自动检测串行数据流是否包括奇偶校验数据，并将串行DTV数据流转换为并行DTV数据流。 如果串行DTV数据流包括奇偶校验数据，则DTV数据格式转换器根据第一转换协议发送从串行DTV数据流转换的并行DTV数据流。 如果串行DTV数据流不包括奇偶校验数据，则转换器根据第二转换协议发送从串行DTV数据流转换的并行DTV数据流。 以这种方式，转换器容纳具有或不具有奇偶校验数据的串行DTV数据流。 DTV数据格式转换器可以以周边组件互连（PCI）卡的形式实现，允许与计算机系统和其他基于PCI的系统的兼容性。 DTV数据格式转换器可以包括接收器块，发送器块和缓冲器。

公开(公告)号：US5963652A

公开(公告)日：1999-10-05

申请号：US667582

申请日：1996-07-12

Applicant: Thanh T. Tran ,  Gokalp Bayramoglu ,  William H. Nott ,  Hiten N. Dalal ,  Conrad M. Allen, Jr.

Inventor： Thanh T. Tran ,  Gokalp Bayramoglu ,  William H. Nott ,  Hiten N. Dalal ,  Conrad M. Allen, Jr.

IPC: H03G1/02 ,  H03G3/00

CPC classification number: H03G1/02

Abstract: A computer system has a speaker, a unit having a central processor, a monitor separate from the unit, a video cable connecting the unit to the monitor, and a volume control for the speaker, the volume control being mounted in the monitor. Circuitry in the unit responds to the volume control by adjusting the volume output of the speaker.

Abstract translation: 计算机系统具有扬声器，具有中央处理器的单元，与该单元分离的监视器，将该单元连接到监视器的视频电缆以及扬声器的音量控制，音量控制装置安装在监视器中。 本机中的电路通过调节扬声器的音量输出来响应音量控制。

公开(公告)号：US5281861A

公开(公告)日：1994-01-25

申请号：US855453

申请日：1992-03-19

Applicant: Thanh T. Tran ,  Clarence Y. Mar ,  Javier F. Izquierdo

Inventor： Thanh T. Tran ,  Clarence Y. Mar ,  Javier F. Izquierdo

IPC: G06F1/10 ,  H03K19/018 ,  H03K5/00 ,  H03B19/00 ,  H03K5/13 ,  H03K7/00

CPC classification number: G06F1/10 ,  H03K19/01806

Abstract: A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.

Abstract translation: 时钟信号分布在电路板上，并以连接器的形式分布在正弦波上。 位于时钟电路附近的电路将正弦波转换成相同的频率方波，供时钟电路使用。 转换器电路的输出级提供高输出电平来驱动CMOS电路。 输出晶体管被上拉至5伏特，但是先前的晶体管被​​上拉至6.3伏，从而补偿基极到发射极的下降。

公开(公告)号：US20100142931A1

公开(公告)日：2010-06-10

申请号：US12330338

申请日：2008-12-08

Applicant: Thanh T. Tran ,  Todd C. Hiers ,  Ivan Garcia ,  Jian Wang

Inventor： Thanh T. Tran ,  Todd C. Hiers ,  Ivan Garcia ,  Jian Wang

IPC: H04N7/01 ,  G09G5/36

CPC classification number: G09G5/363 ,  G09G2320/0252 ,  G09G2360/06 ,  G09G2360/121 ,  G09G2360/18 ,  H04N19/436 ,  H04N19/61

Abstract: A system and method for allocating video processing tasks over multiple video processors include an apparatus. The apparatus includes a plurality of video processors. Each video processor includes a first processor that processes video data and manages buffers used in conversion and displaying video data. The video processor includes a second processor that performs video data signal processing and manages buffers used in processing video data. The apparatus also includes a switch coupled to each video processor, as well as video inputs and video outputs. A third processor coupled to the switch, and a memory coupled to each video processor and to the third processor, are also part of the apparatus. The switch selectively couples a video processor to a video input or a video output, the third processor configures the switch based on processing requirements of each video stream, and the memory buffers and stores video data.

Abstract translation: 用于在多个视频处理器上分配视频处理任务的系统和方法包括一种装置。 该装置包括多个视频处理器。 每个视频处理器包括处理视频数据并管理用于转换和显示视频数据的缓冲器的第一处理器。 视频处理器包括执行视频数据信号处理并管理在处理视频数据中使用的缓冲器的第二处理器。 该装置还包括耦合到每个视频处理器的开关，以及视频输入和视频输出。 耦合到开关的第三处理器和耦合到每个视频处理器和第三处理器的存储器也是该装置的一部分。 开关将视频处理器选择性地耦合到视频输入或视频输出，第三处理器基于每个视频流的处理要求配置开关，并且存储器缓冲并存储视频数据。

公开(公告)号：US07080337B2

公开(公告)日：2006-07-18

申请号：US10749501

申请日：2003-12-31

Applicant: Thanh T. Tran

Inventor： Thanh T. Tran

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  H01L2224/16227 ,  H01L2924/15313 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/185 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: An embodiment of the present invention includes a method of providing a non-uniform distribution of decoupling capacitors to provide a more uniform noise level across the chip. Leads on a packaged semiconductor chip are grouped into two or more regions. Types of leads needing decoupling capacitors are grouped into lead categories. For each region, there may be one or more lead categories therein. One or more decoupling capacitors are preferably assigned to each lead category in each region. Calculations may be performed to estimate a desired capacitance for each decoupling capacitor for each lead category in each region. When a chip has different components operating at different switching frequencies, different voltages, and/or different switching currents, the distribution of the decoupling capacitors will likely be non-uniform to provide a more uniform noise level across the chip, as compared to a uniform distribution of decoupling capacitors for the chip.

Abstract translation: 本发明的实施例包括提供去耦电容器的不均匀分布以在芯片上提供更均匀的噪声电平的方法。 封装的半导体芯片上的引线被分组为两个或更多个区域。 需要去耦电容器的引线类型分为引线类别。 对于每个区域，其中可以有一个或多个引线类别。 一个或多个去耦电容器优选地分配给每个区域中的每个引线类别。 可以执行计算，以估计每个区域中每个引线类别的每个去耦电容器的期望电容。 当芯片具有以不同开关频率，不同电压和/或不同开关电流工作的不同部件时，去耦电容器的分布可能不均匀，以便在整个芯片上提供更均匀的噪声电平，与均匀 芯片去耦电容的分布。

公开(公告)号：US5157277A

公开(公告)日：1992-10-20

申请号：US635721

申请日：1990-12-28

Applicant: Thanh T. Tran ,  David G. Abdoo

Inventor： Thanh T. Tran ,  David G. Abdoo

IPC: G06F1/12 ,  G06F1/10 ,  H03K5/15 ,  H03L7/08

CPC classification number: H03K5/15026 ,  G06F1/10

Abstract: A clock buffer circuit for a computer system, and a computer system incorporating the same, are disclosed. The clock buffer circuit includes a differential input buffer for receiving the input clock signal, with its output coupled to the input of a phase locked loop (PLL). The switching level of the differential input buffer is adjustable, either by adjusting the DC bias applied to the input clock signal, or by adjusting the reference signal, which changes the point in the cycle of the input clock signal at which the differential buffer switches. The PLL synchronizes its output to an edge of the output of the differential buffer, but maintains the same duty cycle (e.g., 50%). Accordingly, the clock buffer circuit may have its delay adjusted, by modifying a voltage divider, applying a variable voltage, or programmably via a digital-to-analog converter, to match the delays of other clock buffer circuits in the computer system, reducing the clock skew in the system. A sine wave may be used as the input clock signal, so that harmonic noise is reduced in the system.

公开(公告)号：US06359987B1

公开(公告)日：2002-03-19

申请号：US08857258

申请日：1997-05-16

Applicant: Thanh T. Tran ,  Hiten N. Dalal ,  Kurtis J. Bowman

Inventor： Thanh T. Tran ,  Hiten N. Dalal ,  Kurtis J. Bowman

IPC: H04R2900

CPC classification number: H04R29/001 ,  H04R5/02 ,  H04S7/308

Abstract: A computer system having automatic speaker detection circuitry is disclosed. The typical computer system includes a central processing unit, a data input device, and a sound card. Further, there is an audio amplifier, as well as an automatic detection and selection circuit that may be within the sound card or the audio amplifier or just part of the computer system as a whole. This automatic detection selection device is able to determine an impedance load of an output device attached to the computer system, namely, a speaker system, and is able to disable the audio amplifier within the computer system upon determining the impedance load and matching that impedance load against a selected value indicating that no amplification of the signal is required for the output device. Further, an audio sound equalizer is part of the system and can be bypassed in the same manner that the audio amplifier is, namely, that particular impedance load is measured indicating that no equalization is necessary.

Abstract translation: 公开了一种具有自动扬声器检测电路的计算机系统。 典型的计算机系统包括中央处理单元，数据输入设备和声卡。 此外，还有一个音频放大器，以及一个自动检测和选择电路，它可能在声卡或音频放大器内，或者只是整个计算机系统的一部分。 该自动检测选择装置能够确定附接到计算机系统（即扬声器系统）的输出装置的阻抗负载，并且能够在确定阻抗负载并匹配该阻抗负载之后禁用计算机系统内的音频放大器 对应于选择的值，指示输出设备不需要放大信号。 此外，音频声音均衡器是系统的一部分，并且可以以与音频放大器相同的方式旁路，即，测量到指示不需要均衡的特定阻抗负载。

公开(公告)号：US06346927B1

公开(公告)日：2002-02-12

申请号：US09183944

申请日：1998-10-31

Applicant: Thanh T. Tran ,  David W. Engler

Inventor： Thanh T. Tran ,  David W. Engler

IPC: G09G500

CPC classification number: G09G5/006

Abstract: A monitor having multiple video input ports and connectors is provided with automatic video input detection/selection circuitry. The circuitry may automatically detect when an external source such as a computer system is driving a video input port. The circuitry, for example, may detect whether a video input port is being driven by monitoring a sync signal (vertical or horizontal) for the video input port. A video input detect signal for a video input port may be generated from the sync signal for the video input port. In response to assertion of the video input detect signal indicating a source is driving a video input port, the circuitry may select the particular video input port. A microcontroller of the circuitry may provide a video input selector signal configured to select the video input port. When a single video input port is driven, user interaction is no longer necessary to select the particular video input port. If multiple video input ports are driven, a user may manually choose a particular video input port through a video selection button provided by an on-screen display of the monitor or by the computer system.

Abstract translation: 具有多个视频输入端口和连接器的监视器具有自动视频输入检测/选择电路。 当诸如计算机系统的外部源驱动视频输入端口时，该电路可以自动检测。 例如，电路可以通过监视视频输入端口的同步信号（垂直或水平）来检测是否正在驱动视频输入端口。 视频输入端口的视频输入检测信号可以从视频输入端口的同步信号产生。 响应于表示源正在驱动视频输入端口的视频输入检测信号的断言，电路可以选择特定的视频输入端口。 电路的微控制器可以提供被配置为选择视频输入端口的视频输入选择器信号。 当单个视频输入端口被驱动时，不再需要用户交互来选择特定的视频输入端口。 如果驱动多个视频输入端口，则用户可以通过由监视器的屏幕显示或计算机系统提供的视频选择按钮手动地选择特定的视频输入端口。

公开(公告)号：US5864811A

公开(公告)日：1999-01-26

申请号：US748268

申请日：1996-11-13

Applicant: Thanh T. Tran ,  John A. Landry ,  Robert F. Watts

Inventor： Thanh T. Tran ,  John A. Landry ,  Robert F. Watts

IPC: G06F3/16 ,  G10H1/00 ,  H04S7/00 ,  G10L9/00

CPC classification number: G10H1/0058 ,  G10H2240/071

Abstract: An audio circuit for a computer includes a bidirectional modem connection, a microphone input, first and second audio output channels, and an audio synthesizing circuit arranged to produce first and second synthesized audio channels. In a first mode of operation the first synthesized audio channel is applied to the first audio output channel and the second synthesized audio channel is applied to the second audio output channel. In a second mode of operation the first and second synthesized audio channels are combined into a monotonic signal and applied to the second audio output channel, and audio signals from the bidirectional modem connection are applied to the first audio output channel.

Abstract translation: 用于计算机的音频电路包括双向调制解调器连接，麦克风输入，第一和第二音频输出通道，以及被配置为产生第一和第二合成音频通道的音频合成电路。 在第一操作模式中，将第一合成音频通道应用于第一音频输出通道，并将第二合成音频通道应用于第二音频输出通道。 在第二操作模式中，第一和第二合成音频通道被组合成单调信号并且被施加到第二音频输出通道，并且来自双向调制解调器连接的音频信号被施加到第一音频输出通道。

公开(公告)号：US5818299A

公开(公告)日：1998-10-06

申请号：US511138

申请日：1995-08-04

Applicant: Thanh T. Tran

Inventor： Thanh T. Tran

IPC: H03G3/34

CPC classification number: H03G3/348

Abstract: An apparatus is described for providing power management of a computer. The apparatus includes circuitry configured to assert a power down signal when a low power mode is to be entered and to de-assert the power down signal when the low power mode is to be exited. An audio amplifier has a power input and a mute input, and a switch is connected to the power input and configured to selectively supply power to the power input. A power down circuit is provided responsive to the power down signal and connected to the mute input and the switch such that when the power down signal is asserted, the power down circuit activates the mute input and subsequently closes the switch, and when the power down signal is de-asserted, the power down circuit open the switch and subsequently deactivates the mute input.

Abstract translation: 描述了一种用于提供计算机的电源管理的装置。 该装置包括被配置为当要输入低功率模式时断言掉电信号并且当要退出低功率模式时解除断电信号的电路。 音频放大器具有电源输入和静音输入，并且开关连接到电源输入并被配置为选择性地向电源输入供电。 断电电路响应于掉电信号被提供并连接到静音输入和开关，使得当掉电信号被断言时，掉电电路激活静音输入并随后闭合开关，并且当掉电 信号被取消置位，掉电电路打开开关，然后停用静音输入。