-
公开(公告)号：US20240067520A1
公开(公告)日：2024-02-29
申请号：US18239986
申请日：2023-08-30
Applicant: Infineon Technologies AG
Inventor： Fabian Streb , Johann Straßer , Hans-Jörg Timme , Marc Füldner , Arnaud Walther , Hutomo Suryo Wasisto
CPC classification number: B81C1/00952 , B81B3/0005 , B81B2203/0127 , B81B2203/0315 , B81B2203/04 , B81C2201/0114 , B81C2201/0133 , B81C2201/0176 , B81C2201/112
Abstract: An encapsulated MEMS device and a method for manufacturing the MEMS device are provided. The method comprises providing a cavity structure having an inner volume comprising a plurality of MEMS elements, which are relatively displaceable with respect to each other, and having an opening structure to the inner volume, depositing a Self-Assembled Monolayer (SAM) through the opening structure onto exposed surfaces within the inner volume of the cavity structure, and closing the cavity structure by applying a layer structure on the opening structure for providing a hermetically closed cavity.
-
公开(公告)号：US20180301344A1
公开(公告)日：2018-10-18
申请号：US15986304
申请日：2018-05-22
Inventor： Lynford Goddard , Kaiyuan Wang , Chris Edwards , Lonna Edwards , Xin Yu , Gang Logan Liu , Samuel Washington , Shailendra Srivastava , Terry Koker , Julianne Lee , Catherine Britt Carlson
IPC: H01L21/306 , H01L31/0236 , C25F3/14 , H01L31/0232 , H01L21/66 , G01B11/24
CPC classification number: H01L21/30604 , B81C1/00103 , B81C1/00111 , B81C1/00119 , B81C1/00214 , B81C1/00484 , B81C1/00539 , B81C1/00595 , B81C2201/0114 , B81C2201/0139 , B81C2201/0157 , C25F3/12 , C25F3/14 , G01B11/2441 , H01L21/30617 , H01L21/3063 , H01L21/76886 , H01L22/12 , H01L31/02327 , H01L31/02363
Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.
-
3.发明申请Quantum-Size-Controlled Photoelectrochemical Etching of Semiconductor Nanostructures 有权半导体纳米结构的量子尺寸控制光电化学蚀刻公开(公告)号：US20150270136A1
公开(公告)日：2015-09-24
申请号：US14624074
申请日：2015-02-17
Applicant: Sandia Corporation
Inventor： Arthur J. Fischer , Jeffrey Y. Tsao , Jonathan J. Wierer, JR. , Xiaoyin Xiao , George T. Wang
IPC: H01L21/306 , H01S5/343 , H01L33/06 , H01L21/3065 , H01L33/00
CPC classification number: H01S5/34333 , B81C1/00539 , B81C2201/0114 , B82B1/00 , C25F3/12 , H01L21/30635 , H01L33/007 , H01L33/18
Abstract: Quantum-size-controlled photoelectrochemical (QSC-PEC) etching provides a new route to the precision fabrication of epitaxial semiconductor nanostructures in the sub-10-nm size regime. For example, quantum dots (QDs) can be QSC-PEC-etched from epitaxial InGaN thin films using narrowband laser photoexcitation, and the QD sizes (and hence bandgaps and photoluminescence wavelengths) are determined by the photoexcitation wavelength.
Abstract translation: 量子尺寸控制光电化学（QSC-PEC）蚀刻提供了一种新的途径，用于在10nm以下的尺寸范围内对外延半导体纳米结构的精密制造。 例如，量子点（QD）可以使用窄带激光光激发从外延InGaN薄膜中进行QSC-PEC蚀刻，并且通过光激发波长确定QD尺寸（因此带隙和光致发光波长）。
-
公开(公告)号：US07433811B2
公开(公告)日：2008-10-07
申请号：US10838859
申请日：2004-05-04
Applicant: Jun Gao , Michael J. Sailor , Sangeeta Bhatia , Christopher Flaim
Inventor： Jun Gao , Michael J. Sailor , Sangeeta Bhatia , Christopher Flaim
CPC classification number: B81C1/00515 , B81C2201/0114 , B81C2201/0115 , C25F3/12 , C25F3/14 , H01L21/3063
Abstract: The invention is directed to methods for direct patterning of silicon. The invention provides the ability to fabricate complex surfaces in silicon with three dimensional features of high resolution and complex detail. The invention is suitable, for example, for use in soft lithography as embodiments of the invention can quickly create a master for use in soft lithography. In an embodiment of the invention, electrochemical etching of silicon, such as a silicon wafer, for example, is conducted while at least a portion of the silicon surface is exposed to an optical pattern. The etching creates porous silicon in the substrate, and removal of the porous silicon layer leaves a three-dimensional structure correlating to the optical pattern.
Abstract translation: 本发明涉及直接图案化硅的方法。 本发明提供了在硅中制造具有高分辨率和复杂细节的三维特征的复杂表面的能力。 本发明适用于例如在软光刻中使用，因为本发明的实施例可以快速地创建用于软光刻的母版。 在本发明的一个实施例中，例如硅的电化学蚀刻被进行，同时硅表面的至少一部分暴露于光学图案。 蚀刻在衬底中产生多孔硅，并且去除多孔硅层留下与光学图案相关的三维结构。
-
公开(公告)号：US06982217B2
公开(公告)日：2006-01-03
申请号：US10391632
申请日：2003-03-20
IPC: H01L21/20 , H01L21/302 , H01L21/461
CPC classification number: H01L21/326 , B81B1/00 , B81B2201/047 , B81C2201/0114 , Y10S977/70
Abstract: A structure having projections is provided. The structure having projections comprises a first projection formed on a first layer containing a first material, and a plurality of second projections formed around the first projection and containing a material capable of being subjected to anodic oxidation.
-
Patent Agency Ranking
公开(公告)号：US20050230839A1
公开(公告)日：2005-10-20
申请号：US11149921
申请日：2005-06-10
Applicant: Michel Despont , Roy Magnuson , Ute Drechsler
Inventor： Michel Despont , Roy Magnuson , Ute Drechsler
IPC: B81B3/00 , B81C1/00 , C23F13/14 , H01L21/306 , H01L21/336
CPC classification number: H01L21/30604 , B81B2201/12 , B81B2203/0118 , B81C1/00801 , B81C2201/0107 , B81C2201/0114 , B81C2201/0133 , C23F13/14
Abstract: A method for protecting a material of a microstructure comprising the material and a noble metal layer against undesired galvanic etching during manufacture, the method comprises forming on the structure a sacrificial metal layer having a lower redox potential than the material, the sacrificial metal layer being electrically connected to the noble metal layer.
Abstract translation: 一种用于在制造期间保护包含该材料的微结构材料和贵金属层以防止不期望的电化学蚀刻的方法，所述方法包括在所述结构上形成具有比所述材料更低的氧化还原电位的牺牲金属层，所述牺牲金属层是电 连接到贵金属层。
-
公开(公告)号：US06949397B2
公开(公告)日：2005-09-27
申请号：US10466516
申请日：2002-01-11
Applicant: Michel Despont , Roy H. Magnuson , Ute Drechsler
Inventor： Michel Despont , Roy H. Magnuson , Ute Drechsler
IPC: B81B3/00 , B81C1/00 , C23F13/14 , H01L21/306 , H01L21/00
CPC classification number: H01L21/30604 , B81B2201/12 , B81B2203/0118 , B81C1/00801 , B81C2201/0107 , B81C2201/0114 , B81C2201/0133 , C23F13/14
Abstract: A method for protecting a material of a microstructure comprising said material and a noble metal layer against undesired galvanic etching during manufacture comprises forming on the structure a sacrificial metal layer having a lower redox potential than said material, the sacrificial metal layer being electrically connected to said noble metal layer.
Abstract translation: 一种用于在制造过程中保护包含所述材料的微结构材料和贵金属层以防止不期望的电镀蚀刻的方法包括在所述结构上形成具有比所述材料更低的氧化还原电位的牺牲金属层，所述牺牲金属层电连接到所述 贵金属层。
-
公开(公告)号：US5525549A
公开(公告)日：1996-06-11
申请号：US49801
申请日：1993-04-21
Applicant: Tsuyoshi Fukada , Yoshimi Yoshino , Yukihiko Tanizawa
Inventor： Tsuyoshi Fukada , Yoshimi Yoshino , Yukihiko Tanizawa
CPC classification number: B81C1/00888 , B81C1/00158 , G01L9/0055 , G01P15/0802 , G01P15/123 , H01L21/3063 , H01L21/78 , B81B2201/0235 , B81C2201/0114 , B81C2201/053 , Y10S148/028 , Y10S148/159 , Y10S438/977
Abstract: A method for producing a semiconductor device that is capable of solving problems related to dicing a metal thin film used for electrochemical etching. According to the method, an n type epitaxial thin layer is formed on a p type single-crystal silicon wafer. An n.sup.+ type diffusion layer is formed in a scribe line area on the epitaxial layer. An n.sup.+ type diffusion layer is formed in an area of the epitaxial layer which corresponds to a predetermined portion of the wafer. An aluminum film is formed over the diffusion layers. The aluminum film has a clearance for passing a dicing blade. Portions of the wafer are electrochemically etched by supplying electricity through the aluminum film and the diffusion layers, to leave portions of the epitaxial layer. The wafer is diced into chips along the scribe line area. Each of the chips forms a separate semiconductor device. The electrochemical etching of the wafer is carried out after the formation of the aluminum film by immersing the wafer in a KOH aqueous solution and by supplying electricity through the aluminum film. The electrochemical etching is terminated at an inflection point where an etching current inflects to a constant level from a peak level. During the electrochemical etching, the diffusion layer reduces horizontal resistance in the epitaxial layer, so that the etched parts receive a sufficient potential to perform the etching.
Abstract translation: 一种能够解决与用于电化学蚀刻的金属薄膜切割相关的问题的半导体器件的制造方法。 根据该方法，在p型单晶硅晶片上形成n型外延薄层。 在外延层上的划线区域中形成n +型扩散层。 在对应于晶片的预定部分的外延层的区域中形成n +型扩散层。 在扩散层上形成铝膜。 铝膜具有用于通过切割刀片的间隙。 通过供电通过铝膜和扩散层对晶片的一部分进行电化学蚀刻，以留下外延层的部分。 晶片沿着划线区切成芯片。 每个芯片形成单独的半导体器件。 通过将晶片浸入KOH水溶液中并通过铝膜供电，在形成铝膜之后进行晶片的电化学蚀刻。 在蚀刻电流从峰值水平变为恒定水平的拐点处终止电化学蚀刻。 在电化学蚀刻期间，扩散层减小外延层中的水平电阻，使得蚀刻部分具有足够的电位进行蚀刻。
-
公开(公告)号：US11970391B2
公开(公告)日：2024-04-30
申请号：US17618198
申请日：2019-12-13
Applicant: Shenzhen Institutes of Advanced Technology
Inventor： Tianzhun Wu , Zhaoling Huang , Qi Zeng
CPC classification number: B81C1/00166 , B81B3/0072 , B81B2201/06 , B81B2203/0172 , B81B2203/04 , B81C2201/0114 , B81C2201/0185 , B81C2201/0187 , B81C2201/0194
Abstract: A method for preparing a flexible electrode is provided. The method comprises sequentially forming a flexible base layer and an intermediate conductive layer on a carrier plate; treating an elastomeric template having an electrode pattern with an acid, followed by transferring and printing the electrode pattern onto the intermediate conductive layer to form an electrode inducing layer; forming a titanium dioxide-polydopamine composite layer in a gap of the electrode inducing layer; forming a platinum electrode layer on the titanium dioxide-polydopamine composite layer; removing the carrier plate. The invention solves the problems of slow formation of a polydopamine film and slow formation of a platinum electrode layer. A flexible electrode is further provided.
-
公开(公告)号：US20180262845A1
公开(公告)日：2018-09-13
申请号：US15918256
申请日：2018-03-12
Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
Inventor： HUI SHI
CPC classification number: H04R19/04 , B81B3/007 , B81B3/0078 , B81B2201/0257 , B81B2203/0127 , B81B2203/0307 , B81B2203/04 , B81C1/00182 , B81C1/00658 , B81C2201/0114 , H04R19/005 , H04R2201/003
Abstract: A microphone includes a substrate, an opening in the substrate, and a support structure in the opening. The support structure includes a first bracket formed in a closed-loop pattern and a second bracket connecting the first bracket to a periphery of the opening. The support structure in the opening increases the mechanical reliability of the microphone.
-
-
-
-
-
-
-
-
-
Search Results
65
records
(took 0.013 seconds)
