公开(公告)号：US20240333431A1

公开(公告)日：2024-10-03

申请号：US18601381

申请日：2024-03-11

Applicant: STMicroelectronics International N.V.

Inventor： Roland Van Der Tuijn ,  Christophe Arnal

IPC: H04L1/1607 ,  H04L5/00

CPC classification number: H04L1/1657 ,  H04L5/0055

Abstract: A method of controlling a receiver of communications includes data packets being transmitted at constant intervals, and circuits of the receiver being, in each interval, set to standby between the correct reception of at least one data packet and a time preceding the beginning of the next interval.

公开(公告)号：US20240333292A1

公开(公告)日：2024-10-03

申请号：US18616951

申请日：2024-03-26

Applicant: STMicroelectronics International N.V.

Inventor： Cao-Thong TU ,  David COUSINARD ,  David CHAMPION ,  Matteo CONTALDO

IPC: H03L7/195 ,  H03L7/081

CPC classification number: H03L7/195 ,  H03L7/0818

Abstract: An electronic device applies a frequency offset function to a first signal having a first frequency. The device includes a delay element configured to output a second signal corresponding to the first signal delayed by a duration equal to a first period of said signal divided by four. A circuit branch includes a first circuit configured to divide the frequency of the first signal by a given number coupled in series with a second circuit configured to implement an integration. The circuit branch outputs a third signal and a fourth signal. A single side band mixing circuit processes the first signal, second signal, third signal and fourth signal to generate an output signal.

公开(公告)号：US20240333175A1

公开(公告)日：2024-10-03

申请号：US18614887

申请日：2024-03-25

Applicant: STMicroelectronics International N.V.

Inventor： Yannick HAGUE ,  Guillaume THIENNOT ,  Romain LAUNOIS

IPC: H02M7/53846 ,  H02M7/5383

CPC classification number: H02M7/538463 ,  H02M7/538466 ,  H02M7/53835

Abstract: A converter circuit is configured to convert a DC voltage into an AC voltage using a first thyristor and second thyristor in series in a first branch, a third thyristor and fourth thyristor in series in a second branch in an antiparallel configuration to the first branch, and a first transistor and second transistor in series in a third branch. When the AC voltage is equal to zero, and when the first thyristor is conductive and the first and second transistors are non-conductive, a first positive current is applied to the gate of the antiparallel third thyristor to control turn on and ensure that the current circulating in the first thyristor falls below the holding current.

公开(公告)号：US20240332406A1

公开(公告)日：2024-10-03

申请号：US18610829

申请日：2024-03-20

Applicant: STMicroelectronics International N.V.

Inventor： Alexis GAUTHIER ,  Pascal CHEVALIER ,  Olivier WEBER ,  Franck ARNAUD

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7394 ,  H01L29/66325

Abstract: A bipolar transistor includes a first PN junction and a second PN junction. A first gate is located on the first PN junction. A second gate is located on the second PN junction.

公开(公告)号：US20240332365A1

公开(公告)日：2024-10-03

申请号：US18614485

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Björn MAGNUSSON LINDGREN ,  Carlo RIVA

IPC: H01L29/16 ,  C30B28/14 ,  C30B29/36 ,  H01L21/02 ,  H01L29/04

CPC classification number: H01L29/1608 ,  C30B28/14 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/0262 ,  H01L29/04

Abstract: Various embodiments of wafers include a polycrystalline silicon carbide (SiC) layer or base substrate. The polycrystalline silicon carbide (SiC) layer may have a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter) such that the polycrystalline silicon carbide layer is a low resistivity polycrystalline silicon carbide layer. The polycrystalline silicon carbide layer may have grains with a grain size less than or equal to 1 millimeter (mm), and may have a non-columnar structure. The polycrystalline silicon carbide layer may have a warpage less than or equal to 75 μm (micrometers). A monocrystalline silicon carbide (SiC) layer may be coupled to the polycrystalline silicon carbide (SiC) layer by a bonding layer. The monocrystalline silicon carbide layer may be thinner than the polycrystalline silicon carbide layer.

公开(公告)号：US20240332328A1

公开(公告)日：2024-10-03

申请号：US18607215

申请日：2024-03-15

Applicant: STMicroelectronics International N.V.

Inventor： Hui-Tzu WANG ,  David GANI ,  Yiying KUO

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14623 ,  H01L24/13 ,  H01L24/14 ,  H01L27/14618 ,  H01L27/14685 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/14051 ,  H01L2224/14183

Abstract: The present disclosure is directed to an optical sensor package with light shielding material covering five sides. The optical sensor package includes a transparent layer, a substrate layer, sensor elements between the transparent layer and the substrate layer, a solder mask on the side of the substrate layer opposite the transparent layer, and layer of molding material covering five sides of the optical sensor package. The solder mask and layer of molding material prevent light from entering the sides of the optical sensor package or from traveling through the substrate layer and reflecting toward the sensor elements.

公开(公告)号：US20240331522A1

公开(公告)日：2024-10-03

申请号：US18191782

申请日：2023-03-28

Applicant: STMicroelectronics International N.V.

Inventor： Federico RIZZARDINI ,  Lorenzo BRACCO

IPC: G08B21/04 ,  G08B29/18

CPC classification number: G08B21/0446 ,  G08B21/043 ,  G08B29/188

Abstract: The present disclosure is directed to a device and method for human fall detection solution. Fall detection is performed by a low power inertial measurement unit (IMU) that is communicatively coupled between a pressure sensor and an application processor. The IMU includes one or more motions sensors, such as an accelerometer and gyroscope. The application processor is the main processor of the containing device. The IMU receives pressure sensor data from the pressure sensor, and executes the fall detection using both the pressure sensor data and accelerometer data.

公开(公告)号：US20240327203A1

公开(公告)日：2024-10-03

申请号：US18613746

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Mark Andrew SHAW ,  Fabio QUAGLIA ,  Domenico GIUSTI ,  Marco FERRERA

IPC: B81B7/00 ,  B81B3/00 ,  B81C1/00 ,  H01L25/18 ,  H10N39/00

CPC classification number: B81B7/007 ,  B81B3/007 ,  B81C1/00301 ,  B81C1/00658 ,  H01L25/18 ,  H10N39/00 ,  B81B2201/0271 ,  B81B2203/0127 ,  B81B2207/012 ,  B81B2207/096 ,  B81C2203/0792

Abstract: A method for manufacturing a MEMS device includes forming a first solid body by forming, on a substrate, a layered structure having a thickness of a value comprised between 4 and 10 μm, with the layered structure having a first surface that is uniformly flat or planar throughout the extension thereof that faces the substrate. The method further includes forming, on a second surface of the layered structure opposite to the first surface in a direction, multiple transducer devices. The method then proceeds with coupling the first solid body to a supporting structure, and completely removing the substrate to expose said uniformly flat or planar surface.

公开(公告)号：US12105145B2

公开(公告)日：2024-10-01

申请号：US18362550

申请日：2023-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Shalini Pathak

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3183

CPC classification number: G01R31/318536 ,  G01R31/317 ,  G01R31/318335 ,  G01R31/31853 ,  G01R31/318533 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318566

Abstract: A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.

公开(公告)号：US20240321809A1

公开(公告)日：2024-09-26

申请号：US18601216

申请日：2024-03-11

Applicant: STMicroelectronics International N.V.

Inventor： Romain COFFY ,  David AUCHERE ,  Vipin VELAYUDHAN

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L24/27 ,  H01L24/29 ,  H01L2224/27318 ,  H01L2224/2741 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2924/151

Abstract: An integrated circuit chip is bonded to a support. The chip includes a first connection pad and two second connection pads. The support includes a third connection pad and two fourth connection pads. A stack layers includes first, second, and third conductive layers and insulating layers. The first, second, and third conductive layers are separated from one another by the insulating layers. The second conductive layer is positioned between the first and third conductive layers. The first and third conductive layers electrically connect the two second connection pads to the two fourth connection pads. The second conductive layer electrically connects the first connection pad to the third connection pad.