公开(公告)号：US08938737B2

公开(公告)日：2015-01-20

申请号：US13605412

申请日：2012-09-06

Applicant: Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard A. Uhlig ,  Udo Steinberg ,  Sebastian Schoenberg ,  Sridhar Muthrasanallur ,  Steven M. Bennett ,  Andrew V. Anderson ,  Erik C. Cota-Robles

Inventor： Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard A. Uhlig ,  Udo Steinberg ,  Sebastian Schoenberg ,  Sridhar Muthrasanallur ,  Steven M. Bennett ,  Andrew V. Anderson ,  Erik C. Cota-Robles

IPC: G06F9/455 ,  G06F13/24 ,  G06F13/26 ,  G06F9/48

CPC classification number: G06F13/24 ,  G06F9/45533 ,  G06F9/4812

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract translation: 公开了用于向虚拟处理器递送中断的装置，方法和系统的实施例。 在一个实施例中，装置包括用于接收中断请求，传递逻辑和退出逻辑的接口。 交付逻辑是基于中断请求的属性来确定中断请求是否被传送到虚拟处理器。 如果传递逻辑确定中断请求不被传送到虚拟处理器，则出口逻辑是将控制传送到主机。

公开(公告)号：US20140365696A1

公开(公告)日：2014-12-11

申请号：US14467604

申请日：2014-08-25

Applicant: Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

Inventor： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F9/4812

Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic. and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

Abstract translation: 公开了向虚拟处理器发布中断的系统，装置和方法的实施例。 在一个实施例中，一种装置包括查找逻辑。 和发布逻辑。 查找逻辑是在数据结构中查找与中断请求相关联的条目给虚拟处理器。 发布逻辑是将中断请求发布在由第一数据结构中的信息指定的数据结构中。

公开(公告)号：US20140344553A1

公开(公告)日：2014-11-20

申请号：US13898189

申请日：2013-05-20

Applicant: Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

Inventor： Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345

Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

Abstract translation: 根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

公开(公告)号：US08843727B2

公开(公告)日：2014-09-23

申请号：US10957306

申请日：2004-09-30

Applicant: Ioannis Schoinas ,  Gilbert Neiger ,  Rajesh Madukkarumukumana ,  Ku-jei King ,  Richard Uhlig ,  Achmed Rumi Zahir ,  Koichi Yamada

Inventor： Ioannis Schoinas ,  Gilbert Neiger ,  Rajesh Madukkarumukumana ,  Ku-jei King ,  Richard Uhlig ,  Achmed Rumi Zahir ,  Koichi Yamada

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1081 ,  G06F12/1036 ,  G06F12/109

Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.

Abstract translation: 本发明的一个实施例是一种增强地址转换性能的技术。 寄存器存储用于指示由芯片组中的电路支持的能力指示符，用于将客体物理地址地址转换为主机物理地址。 在地址转换中使用多个多级页表进行页面行走。 每个页表都有页表项。 每个页表条目至少具有与能力指示符指示的能力对应的条目说明符。

公开(公告)号：US08813077B2

公开(公告)日：2014-08-19

申请号：US13590001

申请日：2012-08-20

Applicant: Steven Bennett ,  Andrew Anderson ,  Gilbert Neiger ,  Scott Rodgers ,  Richard Uhlig ,  Lawrence Smith, III ,  Barry Huntley

Inventor： Steven Bennett ,  Andrew Anderson ,  Gilbert Neiger ,  Scott Rodgers ,  Richard Uhlig ,  Lawrence Smith, III ,  Barry Huntley

IPC: G06F9/455 ,  G06F9/46 ,  G06F13/24 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/45533 ,  G06F9/3861 ,  G06F9/45545 ,  G06F9/4555 ,  G06F9/45558 ,  G06F9/4812 ,  G06F9/542 ,  G06F13/24 ,  G06F2009/45566

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract translation: 公开了在分层虚拟化架构中处理虚拟化事件的装置和方法的实施例。 在一个实施例中，装置包括事件逻辑和评估逻辑。 事件逻辑是识别虚拟化事件。 评估逻辑是为了响应于虚拟化事件来确定是否将控制从子客户端传送到父访客。

公开(公告)号：US20140053155A1

公开(公告)日：2014-02-20

申请号：US14060947

申请日：2013-10-23

Applicant: Erik C. Cota-Robles ,  Gilbert Neiger ,  Steven M. Bennett ,  Andrew V. Anderson

Inventor： Erik C. Cota-Robles ,  Gilbert Neiger ,  Steven M. Bennett ,  Andrew V. Anderson

IPC: G06F9/455

CPC classification number: G06F9/45533 ,  G06F9/455 ,  G06F9/45558 ,  G06F9/46 ,  G06F9/461 ,  G06F9/462 ,  G06F9/468 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/348 ,  G06F2009/45591 ,  G06F2201/815 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: Embodiments of apparatuses, methods, and systems for virtualizing performance counters are disclosed. In one embodiment, an apparatus includes a counter, a counter enable storage location, counter enable logic, and virtual machine control logic. The counter enable storage location is to store a counter enable indicator. The counter enable logic is to enable the counter based on the counter enable indicator. The virtual machine control logic is to transfer control of the apparatus to a guest. The virtual machine control logic includes guest state load logic to cause a guest value from a virtual machine control structure to be loaded into the counter enable storage location in connection with a transfer of control of the apparatus to the guest.

Abstract translation: 公开了用于虚拟化性能计数器的装置，方法和系统的实施例。 在一个实施例中，装置包括计数器，计数器使能存储位置，计数器使能逻辑和虚拟机器控制逻辑。 计数器使能存储位置是存储计数器使能指示符。 计数器使能逻辑是基于计数器使能指示器启用计数器。 虚拟机控制逻辑是将设备的控制传送给客人。 虚拟机控制逻辑包括客户端状态负载逻辑，以使来自虚拟机控制结构的客户值被加载到计数器使能存储位置中，并将该设备的控制转移给客户端。

公开(公告)号：US20130326519A1

公开(公告)日：2013-12-05

申请号：US13995317

申请日：2011-12-30

Applicant: Andrew V. Anderson ,  Gilbert Neiger ,  Scott D. Rodgers ,  Lawrence O. Smith, III ,  Richard A. Uhlig ,  Steven M. Bennett

Inventor： Andrew V. Anderson ,  Gilbert Neiger ,  Scott D. Rodgers ,  Lawrence O. Smith, III ,  Richard A. Uhlig ,  Steven M. Bennett

IPC: G06F9/455

CPC classification number: G06F9/45533

Abstract: Embodiments of apparatuses and methods for processing virtual machine control structure shadowing are disclosed. In one embodiment, an apparatus includes instruction hardware, execution hardware, and control logic. The instruction hardware is to receive instructions. A first instruction is to transfer the processor from a root mode to a non-root mode. The non-root mode is for executing guest software in a virtual machine, where the processor is the return to root mode upon the detection of a virtual machine exit event. A second instruction is to access a data structure for controlling a virtual machine. The execution hardware is to execute the instructions. The control logic is to cause the processor to access a shadow data structure instead of the data structure, without returning to the root mode for the access to be performed, when the second instruction is executed in the non-root mode.

Abstract translation: 公开了用于处理虚拟机控制结构阴影的装置和方法的实施例。 在一个实施例中，装置包括指令硬件，执行硬件和控制逻辑。 指令硬件是接收指令。 第一条指令是将处理器从根模式转移到非根模式。 非根模式用于在虚拟机中执行客户软件，其中处理器在检测虚拟机退出事件时返回到根模式。 第二条指令是访问用于控制虚拟机的数据结构。 执行硬件是执行指令。 当以非根模式执行第二指令时，控制逻辑是使处理器不用返回到执行访问的根模式而不是数据结构而不是数据结构。

公开(公告)号：US08561068B2

公开(公告)日：2013-10-15

申请号：US13290798

申请日：2011-11-07

Applicant: Steven M. Bennett ,  Andrew V. Anderson ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig ,  Xiang Zou ,  Lawrence Smith ,  Scott Rodgers

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig ,  Xiang Zou ,  Lawrence Smith ,  Scott Rodgers

IPC: G06F9/455 ,  G06F9/46

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F2009/45583

Abstract: In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.

Abstract translation: 在一个实施例中，识别相对于一个或多个虚拟机（VM）的虚拟机监视器（VMM）的预定义行为，并且基于所述一个或多个虚拟机（VM）的预定义行为来利用与所述一个或多个VM相关联的处理器管理的资源 VMM。

公开(公告)号：US20130232288A1

公开(公告)日：2013-09-05

申请号：US13837730

申请日：2013-03-15

Applicant: Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

Inventor： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F9/4812

Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

Abstract translation: 公开了向虚拟处理器发布中断的系统，装置和方法的实施例。 在一个实施例中，装置包括查找逻辑和发布逻辑。 查找逻辑是在数据结构中查找与中断请求相关联的条目给虚拟处理器。 发布逻辑是将中断请求发布在由第一数据结构中的信息指定的数据结构中。

公开(公告)号：US20130212314A1

公开(公告)日：2013-08-15

申请号：US13837997

申请日：2013-03-15

Applicant: Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

Inventor： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4843 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1063 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/30 ,  G06F2212/50 ,  G06F2212/604 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.