公开(公告)号：US20240248874A1

公开(公告)日：2024-07-25

申请号：US18157437

申请日：2023-01-20

Applicant: Dell Products L.P.

Inventor： Sunil Yadav ,  Shelesh Chopra

IPC: G06F16/11 ,  G06F11/14

CPC classification number: G06F16/122 ,  G06F11/1456 ,  G06F11/1469 ,  G06F2201/885

Abstract: Techniques described herein relate to a method for performing data protection of file system data on a host. The method includes identifying, by a data protection agent, a backup access event associated with a backup of a file system stored on a backup storage; in response to identifying the backup access event: obtaining backup metadata associated with the backup from a data protection manager; generating a placeholder file system using the backup metadata and storing the placeholder file system in virtual hard disk file; loading the virtual hard disk file on a target application; performing, after the loading, prefetching of backup data using the virtual hard disk file and the backup metadata to store the backup data in a cache; and performing backup access services using the virtual hard disk file, the backup metadata, and the cache.

公开(公告)号：US20240184688A1

公开(公告)日：2024-06-06

申请号：US18553820

申请日：2022-04-18

Applicant: Microsoft Technology Licensing, LLC

Inventor： Jordi MOLA

IPC: G06F11/36 ,  G06F11/30 ,  G06F12/0891

CPC classification number: G06F11/3636 ,  G06F11/3037 ,  G06F12/0891 ,  G06F2201/885

Abstract: Using memory markings to record plural execution contexts into independent traces. A processor detects a memory operation and identifies an associated memory marking from among a first marking indicating that a first memory region is logged for the first context, and a second marking indicating that a second memory region is logged for a second context. Based on identifying the memory marking as the second marking, and based the first context causing the memory operation, the processor performs at least one of: when the memory operation causes an influx into a cache, logging the influx to a second trace associated with the second context; when the memory operation is a read, logging the read to a first trace associated with the first context; or when the memory operation is a write, performing one of logging the write to the second trace, or evicting a target cache line.

公开(公告)号：US20240095185A1

公开(公告)日：2024-03-21

申请号：US18548318

申请日：2022-03-21

Applicant: Microsoft Technology Licensing, LLC

Inventor： Jordi MOLA

IPC: G06F12/1045 ,  G06F11/34 ,  G06F12/0811

CPC classification number: G06F12/1045 ,  G06F11/3471 ,  G06F12/0811 ,  G06F2201/885

Abstract: Compressing memory addresses within an execution trace via reference to a translation lookaside buffer (TLB) entry. A microprocessor identifies a TLB entry within a TLB slot, the TLB entry mapping a virtual memory page to a physical memory page. The microprocessor initiates logging of the TLB entry by initiating logging of at least a virtual address of the virtual memory page, and an identifier that uniquely identifies the TLB entry from among a plurality of live TLB entries. Subsequently, the microprocessor identifies a cache entry within a memory cache slot, the cache entry comprising a physical memory address corresponding to a cache line. The microprocessor initiates logging of the cache entry by matching a physical memory page identification portion of the physical memory address with the TLB entry, and then initiates logging of at least the identifier for the TLB entry and an offset portion.

公开(公告)号：US20240086329A1

公开(公告)日：2024-03-14

申请号：US18470553

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Vasileios Porpodas ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Wei-Yu Chen

IPC: G06F12/0862 ,  G06F8/41 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F12/0862 ,  G06F8/41 ,  G06F8/4442 ,  G06F9/30047 ,  G06F12/0875 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/502 ,  G06F2212/602 ,  G06F2212/6028

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

公开(公告)号：US11803476B2

公开(公告)日：2023-10-31

申请号：US17210867

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Vasileios Porpodas ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Wei-Yu Chen

IPC: G06F12/0862 ,  G06F12/0875 ,  G06F9/30 ,  G06F8/41

CPC classification number: G06F12/0862 ,  G06F8/41 ,  G06F8/4442 ,  G06F9/30047 ,  G06F12/0875 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/502 ,  G06F2212/602 ,  G06F2212/6028

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

公开(公告)号：US10082968B2

公开(公告)日：2018-09-25

申请号：US15144044

申请日：2016-05-02

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Clark Edward Lubbers ,  Robert Michael Lester

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/36 ,  G06F12/08 ,  G06F11/34 ,  G06F12/0866

CPC classification number: G06F3/0619 ,  G06F3/0605 ,  G06F3/0617 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/067 ,  G06F11/3433 ,  G06F11/3485 ,  G06F12/0866 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885

Abstract: A data storage system and associated method are provided wherein a policy engine continuously collects qualitative information about a network load to the data storage system in order to dynamically characterize the load and continuously correlates the load characterization to the content of a command queue of transfer requests for writeback commands and host read commands, selectively limiting the content with respect to writeback commands to only those transfer requests for writeback data that are selected on a physical zone basis of a plurality of predefined physical zones of a storage media.

公开(公告)号：US20180196727A1

公开(公告)日：2018-07-12

申请号：US15402412

申请日：2017-01-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. GIAMEI ,  Christian JACOBI ,  Daniel V. ROSA ,  Anthony SAPORITO ,  Donald W. SCHMIDT

IPC: G06F11/34 ,  G06F9/48 ,  G06F11/30

CPC classification number: G06F11/3433 ,  G06F9/4881 ,  G06F9/5033 ,  G06F11/3024 ,  G06F11/3419 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2209/508

Abstract: A facility is provided for collecting time-slice-instrumentation information during processing unit execution. The facility counts, at least in part, occurrence of a specified processing unit event during a time-slice of processing unit execution. The counted events occurring during a first interval of execution and a second interval of execution of the time-slice are retained. The first interval of execution is earlier in the time-slice than the second interval of execution, and the counted events facilitate adjusting performance of the processing unit. In an embodiment, the time-slice is a contiguous period of time of processing unit execution, and the specified processing unit event includes a cache event. The processing unit may interleave processing of multiple different units of work across multiple contiguous time-slices, and during a single time-slice, a single unit of work of the multiple different units of work is processed by the processing unit.

公开(公告)号：US10007614B2

公开(公告)日：2018-06-26

申请号：US15013139

申请日：2016-02-02

Applicant: Cavium, Inc.

Inventor： Xiaodong Wang ,  Srilatha Manne ,  Bryan Wai Chin ,  Isam Akkawi ,  David Asher

IPC: G06F12/0888 ,  G06F12/1045

CPC classification number: G06F12/1045 ,  G06F11/3065 ,  G06F12/0811 ,  G06F12/126 ,  G06F2201/885 ,  G06F2212/1021 ,  G06F2212/1048 ,  G06F2212/502

Abstract: System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result; comparing the count value for the at least one tracked attribute with a threshold associated with the at least one tracked attribute; assigning the metric of sticky property to a cache line corresponding to the translation look-aside buffer entry when the count value for at least one of the at least one tracked attribute exceeds the threshold. Selective caching then assigns different protection status to the cache lines with and without sticky property; and evicting a cache line in accordance with a cache eviction policy starting with the cache lines with the lowest protection status.

公开(公告)号：US10001996B2

公开(公告)日：2018-06-19

申请号：US13662171

申请日：2012-10-26

Applicant: NVIDIA Corporation

Inventor： Magnus Ekman ,  James van Zoeren ,  Paul Serris

IPC: G06F9/38 ,  G06F9/30 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/30189 ,  G06F9/3842 ,  G06F11/3024 ,  G06F11/3409 ,  G06F2201/885

Abstract: Embodiments related to selecting a runahead poison policy from a plurality of runahead poison policies during microprocessor operation are provided. The example method includes causing the microprocessor to enter runahead upon detection of a runahead event and implementing a first runahead poison policy selected from a plurality of runahead poison policies operative to manage runahead poison injection during runahead. The example method also includes during microprocessor operation, selecting a second runahead poison policy operative to manage runahead poison injection differently from the first runahead poison policy.

公开(公告)号：US20180165205A1

公开(公告)日：2018-06-14

申请号：US15373701

申请日：2016-12-09

Applicant: INTEL CORPORATION

Inventor： Ruchira Sasanka

IPC: G06F12/0864 ,  G11C7/10 ,  G06F12/0811 ,  G06F12/0808 ,  G06F12/128

CPC classification number: G06F12/0864 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F2201/885 ,  G06F2212/1021 ,  G06F2212/601

Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.