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    CIRCUIT BOARD STRUCTURE
    91.
    发明申请
    CIRCUIT BOARD STRUCTURE 审中-公开
    电路板结构

    公开(公告)号：US20160372409A1

    公开(公告)日：2016-12-22

    申请号：US14742098

    申请日：2015-06-17

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Jaen-Don Lan ,  PIN-CHUNG LIN ,  CHEN-RUI TSENG ,  CHENG-EN HO ,  YU-AN CHEN

    IPC: H01L23/498

    CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894

    Abstract: Disclosed is a circuit board structure, including the first, second and third metal layers sequentially stacked on the substrate from bottom to top and formed by the sputtering process, the chemical plating process and the electroplating process, respectively. The substrate includes the stop layer and the resin layer stacked on the stop layer. The stop layer includes a pattern having at least one contact region, which is not covered by the resin layer. The first, second and third metal layers have an etched circuit pattern, respectively, and each of the etched circuit patterns is provided out of the corresponding contact region and aligned to each other to expose part of the resin layer. The etched circuit pattern is used for electrical connection. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and more stable.

    Abstract translation: 公开了一种电路板结构，其包括分别从底部到顶部依次层叠在基板上的第一，第二和第三金属层，并通过溅射工艺，化学镀工艺和电镀工艺形成。 基板包括停止层和层叠在停止层上的树脂层。 止挡层包括具有至少一个不被树脂层覆盖的接触区域的图案。 第一，第二和第三金属层分别具有蚀刻电路图案，并且每个蚀刻电路图案被提供在相应的接触区域之外并且彼此对准以暴露部分树脂层。 蚀刻电路图案用于电连接。 由于第一金属层提供优异的表面性质，所以第二和第三金属层是良好固定的并且更稳定。

    Stacked multilayer structure
    94.
    发明授权
    Stacked multilayer structure 有权
    堆叠多层结构

    公开(公告)号：US09095084B2

    公开(公告)日：2015-07-28

    申请号：US13853303

    申请日：2013-03-29

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Ting-Hao Lin ,  Yu-Te Lu ,  De-Hao Lu

    IPC: H05K1/00 ,  H05K1/09 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H05K3/38

    CPC classification number: H05K3/4647 ,  H05K1/0366 ,  H05K3/38

    Abstract: A stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed.

    Abstract translation: 一种堆叠多层结构，包括具有凸起的第一电路层，堆叠在第一电路层上以填充凸块之间的空间以形成共面的塑料膜，以及形成在共面上的第二电路层 并连接到第一电路层。 该塑料膜包括嵌入并不暴露的玻璃纤维层。

    METHOD OF MANUFACTURING A THIN SUPPORT PACKAGE STRUCTURE
    95.
    发明申请
    METHOD OF MANUFACTURING A THIN SUPPORT PACKAGE STRUCTURE 有权
    制造薄支撑包装结构的方法

    公开(公告)号：US20150044359A1

    公开(公告)日：2015-02-12

    申请号：US13960123

    申请日：2013-08-06

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Hsueh-Ping Chien ,  Jun-Chung Hsu

    IPC: H05K3/46 ,  H05K3/00 ,  H05K3/40

    CPC classification number: H05K3/4682 ,  H05K3/007 ,  H05K3/22 ,  H05K2201/2009 ,  H05K2203/0165 ,  H05K2203/0169 ,  H05K2203/162

    Abstract: A method of manufacturing a thin support package structure includes the steps of: preparing a support plate formed with a plurality of grooves adjacent to an outer rim thereof, forming a releasing material layer on the support plate; forming a first circuit layer on the releasing material layer so as to form a thin circuit board; forming a dielectric layer on the releasing material layer; forming a plurality of openings in the dielectric layer; forming a second circuit layer on the dielectric layer; forming connection plugs by filling the openings; forming a solder mask on the dielectric layer; forming a plurality of notches on the lower surface of the support plate to communicate with the grooves, respectively; and removing the central part of the support plate between the notches and the central part of the releasing material on the support plate.

    Abstract translation: 制造薄支撑包装结构的方法包括以下步骤：制备形成有与其外缘相邻的多个槽的支撑板，在支撑板上形成释放材料层; 在所述释放材料层上形成第一电路层以形成薄电路板; 在释放材料层上形成介电层; 在介电层中形成多个开口; 在所述电介质层上形成第二电路层; 通过填充开口形成连接插头; 在电介质层上形成焊料掩模; 在所述支撑板的下表面上分别形成多个凹槽以与所述凹槽连通; 并且将支撑板的中心部分移除在支撑板上的切口和释放材料的中心部分之间。

    METHOD OF PACKAGING A CHIP AND A SUBSTRATE
    97.
    发明申请
    METHOD OF PACKAGING A CHIP AND A SUBSTRATE 审中-公开
    包装芯片和基板的方法

    公开(公告)号：US20140295623A1

    公开(公告)日：2014-10-02

    申请号：US13853255

    申请日：2013-03-29

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Ting-Hao Lin ,  Yu-Te Lu ,  De-Hao Lu

    IPC: H01L21/56

    CPC classification number: H01L21/4846 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/562 ,  H01L2221/68345 ,  H01L2224/73204

    Abstract: Disclosed is a method of packaging a chip and a substrate, including the steps of forming a substrate with a thickness ranging from 70 to 150 μm, which comprises a dielectric layer, a circuit metal layer stacked on the dielectric layer and bonding pads higher than the dielectric layer by 10 to 15 μm; forming a stabilizing structure around the substrate to provide a receiving space; disposing the chip on the receiving space and bonding the pins of the chip with the bonding pads; and filling up the receiving space under the chip with a filling material to a total thickness ranging from 300 to 850 μm. Without the plastic molding process, the present invention reduces the cost and the total thickness, and further prevents the substrate from warping by use of the stabilizing fixing structure.

    Abstract translation: 公开了一种封装芯片和基板的方法，包括以下步骤：形成厚度范围为70-150μm的基板，该基板包括介电层，堆叠在电介质层上的电路金属层和高于 介电层10〜15μm; 在所述基板周围形成稳定结构以提供接收空间; 将芯片放置在接收空间上，并将芯片的引脚与焊盘接合; 并用填充材料填充芯片下方的接收空间，总厚度为300至850μm。 没有塑料成型工艺，本发明降低了成本和总厚度，并且通过使用稳定固定结构进一步防止了基板翘曲。

    Laminate circuit board with a multi-layer circuit structure
    98.
    发明授权
    Laminate circuit board with a multi-layer circuit structure 有权
    层压电路板具有多层电路结构

    公开(公告)号：US08754328B2

    公开(公告)日：2014-06-17

    申请号：US13663141

    申请日：2012-10-29

    Applicant: Kinsus Interconnect Technology Corp.

    Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

    IPC: H02G15/00 ,  H05K1/11

    CPC classification number: H05K3/28 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0347

    Abstract: A laminate circuit board with a multi-layer circuit structure which includes a substrate, a first circuit metal layer, a second circuit metal layer, a first nanometer plating layer, a second nanometer plating layer and a cover layer is disclosed. The first circuit metal layer is embedded in the substrate or formed on at least one surface of the substrate which is smooth. The first nanometer plating layer with a smooth surface covers the first circuit metal layer. The second nanometer plating layer is formed on the other surface of the substrate and fills up the opening in the cover layer to electrically connect the first circuit metal layer. The junction adhesion is improved by the chemical bonding between the nanometer plating layer and the cover layer/the substrate. Therefore, the circuit metal layer does not need to be roughened and the density of the circuit increases.

    Abstract translation: 公开了一种具有多层电路结构的叠层电路板，其包括基板，第一电路金属层，第二电路金属层，第一纳米镀层，第二纳米镀层和覆盖层。 第一电路金属层嵌入衬底中或形成在衬底的平滑的至少一个表面上。 具有光滑表面的第一纳米镀层覆盖第一电路金属层。 第二纳米镀层形成在基板的另一个表面上，并填满覆盖层中的开口以电连接第一电路金属层。 通过纳米电镀层和覆盖层/基板之间的化学键合来改善连接粘附。 因此，电路金属层不需要粗糙化，电路密度增加。

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