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    Semiconductor memory device having self-precharge function
    91.
    发明申请
    Semiconductor memory device having self-precharge function 失效
    具有自放电功能的半导体存储器件

    公开(公告)号：US20040233764A1

    公开(公告)日：2004-11-25

    申请号：US10706964

    申请日：2003-11-14

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Mitsuya Kinoshita ,  Hideyuki Noda

    IPC: G11C008/00

    CPC classification number: G11C11/4094 ,  G11C7/12 ,  G11C2207/005

    Abstract: In a semiconductor memory device having a shared sense amplifier configuration, a control circuit outputting a-bit line isolation signal latches a block selection signal in accordance with a change in a trigger signal. With this configuration, when the same block is selected, no change is caused in the bit line isolation signal. Consequently, charge/discharge current is reduced, and power consumption is reduced. Since a specific bit in a refresh counter is not used, unlike the conventional technique, the design changes little even in the case of changing the configuration of an array.

    Abstract translation: 在具有共享读出放大器配置的半导体存储器件中，输出位位线隔离信号的控制电路根据触发信号的变化来锁存块选择信号。 利用该配置，当选择相同的块时，在位线隔离信号中不会发生改变。 因此，充放电电流降低，功耗降低。 由于不使用刷新计数器中的特定位，与传统技术不同，即使在改变阵列的配置的情况下，设计也变化很小。

    Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit
    92.
    发明申请
    Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit 失效
    时钟发生电路能够设置或控制时钟信号的占空比，包括时钟发生电路的系统

    公开(公告)号：US20040232967A1

    公开(公告)日：2004-11-25

    申请号：US10682166

    申请日：2003-10-10

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Koichi Ishimi

    IPC: G06F001/04

    CPC classification number: G06F1/08 ,  H03K5/1565 ,  H03K7/08

    Abstract: A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty ratio of at least one of the clock signals can be varied.

    Abstract translation: 时钟发生电路接收用于向外围电路输出时钟信号的参考时钟信号。 包括在时钟生成电路中的从缓冲电路输出的输出缓冲器信号中的至少一个的占空比被改变，使得可以改变至少一个时钟信号的占空比。

    Semiconductor device and manufacturing method thereof
    93.
    发明申请
    Semiconductor device and manufacturing method thereof 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20040232512A1

    公开(公告)日：2004-11-25

    申请号：US10874363

    申请日：2004-06-24

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Eiji Hasunuma ,  Hideki Genjo ,  Shigeru Shiratake ,  Atsushi Hachisuka ,  Koji Taniguchi

    IPC: H01L021/336 ,  H01L029/40

    CPC classification number: H01L27/10852 ,  H01L21/28568 ,  H01L21/76814 ,  H01L21/76831 ,  H01L27/10808

    Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

    Abstract translation: 在半导体装置中，为了满足半导体装置的小型化使接触孔的直径减小的要求，没有被氢氟酸腐蚀的抗HF侧壁膜由隔离膜形成，例如 氮化物膜设置在接触孔的侧壁上。 此外，在接触孔下端附近的硅衬底1中设置有连接到一对n型源极/漏极区域中的一个和到达p型隔离区域的第一杂质区域的第二杂质区域。 由于这种结构，可以根据小型半导体器件的需要防止用于形成互连层的直径的膨胀，因此可以提供稳定半导体器件的操作特性的半导体器件及其制造方法。

    Semiconductor device with dummy electrode
    95.
    发明申请
    Semiconductor device with dummy electrode 有权
    具有虚拟电极的半导体器件

    公开(公告)号：US20040232444A1

    公开(公告)日：2004-11-25

    申请号：US10716614

    申请日：2003-11-20

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Satoshi Shimizu

    IPC: H01L029/76

    CPC classification number: H01L27/11521 ,  H01L21/76897 ,  H01L27/115 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact portion extending, when viewed from above, parallel to the straight portion. The longer side of the rectangle defined by the linear contact portion is, when viewed from above, located beyond the sidewall insulating film and within the top region of the gate electrode and the dummy electrode. A gap G between the gate electrode and the dummy electrode appearing, when viewed from above, in the linear contact portion is filled with the sidewall insulating film such that the semiconductor substrate is not exposed.

    Abstract translation: 一种半导体器件包括：具有直线部分的栅极电极，位于直线部分延伸点上的虚拟电极，阻挡绝缘膜，侧壁绝缘膜，层间绝缘膜和延伸的线性接触部分 从上方观察，平行于直线部分。 当从上方观察时，由线性接触部分限定的矩形的长边位于侧壁绝缘膜之外并且位于栅电极和虚拟电极的顶部区域内。 当从上方观察时，在直线接触部分中出现的栅电极和虚拟电极之间的间隙G被填充有侧壁绝缘膜，使得半导体衬底不暴露。

    Automatic floor-planning method capable of shortening floor-plan processing time
    96.
    发明申请
    Automatic floor-planning method capable of shortening floor-plan processing time 有权
    自动楼层规划方法能够缩短平面图处理时间

    公开(公告)号：US20040228167A1

    公开(公告)日：2004-11-18

    申请号：US10836324

    申请日：2004-05-03

    Applicant: Renesas Technology Corp.

    Inventor： Ken Saito ,  Yoshio Inoue ,  Koji Hirakimoto

    IPC: G11C011/00

    CPC classification number: G06F17/5072 ,  H01L27/0203

    Abstract: An automatic floor-planning method includes extracting a register and a logic operation cell in a semiconductor integrated-circuit unit, extracting a first register set and a second register set that are assumed to input and receive a signal to and from the logic operation cell directly or via other logic operation cell, respectively, creating a set of the logic operation cells as a cluster cell, determining a layout of the cluster cell and the register, selecting a logic level block for which a floor plan is performed, and determining an arrangement and wiring area such that the arrangement and wiring area of the logic level block includes as many cells as possible that belong to the logic level block.

    Abstract translation: 自动楼层规划方法包括提取半导体集成电路单元中的寄存器和逻辑运算单元，提取假设为直接从逻辑运算单元输入和接收信号的第一寄存器组和第二寄存器组 或经由其他逻辑运算单元，创建一组逻辑运算单元作为集群单元，确定集群单元和寄存器的布局，选择执行平面图的逻辑电平块，以及确定布置 和布线区域，使得逻辑电平块的布置和布线区域包括属于逻辑电平块的尽可能多的单元。

    Packet communication device sending delayed acknowledgement through network
    97.
    发明申请
    Packet communication device sending delayed acknowledgement through network 审中-公开
    分组通信设备通过网络发送延迟确认

    公开(公告)号：US20040223506A1

    公开(公告)日：2004-11-11

    申请号：US10431460

    申请日：2003-05-08

    Applicant: Renesas Technology Corp.

    Inventor： Go Sato

    IPC: H04L012/54

    CPC classification number: H04L47/34 ,  H04L1/1809 ,  H04L47/10 ,  H04L47/193 ,  H04L47/323 ,  H04L69/16 ,  H04L69/163

    Abstract: A switching function determines whether to use delayed acknowledgment in following processing on the basis of whether received data is a nullsuccessivenull or nullnon-successivenull type of data. That is, when the type of the received data is nullsuccessive,null delayed acknowledgment is basically used in the processing. On the other hand, when the type of the received data is nullnon-successive,null delayed acknowledgment is basically not used. When the received data is nullnon-successive,null a normal receiving processing is performed according to TCP.

    Abstract translation: 切换功能基于接收数据是否是“连续”或“非连续”类型的数据来确定在后续处理中是否使用延迟确认。 也就是说，当接收到的数据的类型是“连续的”时，在处理中基本上使用延迟确认。 另一方面，当接收到的数据的类型是“不连续”时，基本上不使用延迟确认。 当接收到的数据是“不连续的”时，根据TCP执行正常的接收处理。

    Semiconductor device
    99.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20040217802A1

    公开(公告)日：2004-11-04

    申请号：US10851156

    申请日：2004-05-24

    Applicant: Renesas Technology Corp.

    Inventor： Kiyoo Itoh ,  Hiroyuki Mizuno

    IPC: H03K003/01

    CPC classification number: G11C5/146 ,  G05F3/205 ,  G11C5/147 ,  H01L27/092 ,  H02M3/073 ,  H03K19/0013 ,  H03K19/0016 ,  H03K19/00315

    Abstract: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.

    Abstract translation: 当电源接通时，在正常操作期间以及当电源电压被切断时，控制具有低阈值电压MOSFET的CMOS电路的阱电压。 因此，CMOS电路可以以更低的功耗稳定地运行，因为当将电源电压施加到CMOS电路时或者当电源电压被切断时，锁存减小，并且在正常操作期间亚阈值电流减小。

    Non-volatile semiconductor memory device and manufacturing method therefor
    100.
    发明申请
    Non-volatile semiconductor memory device and manufacturing method therefor 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20040217411A1

    公开(公告)日：2004-11-04

    申请号：US10859122

    申请日：2004-06-03

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Jun Ohtani ,  Tsukasa Ooishi

    IPC: H01L029/76

    CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    Abstract: A non-volatile semiconductor memory device of the present invention is provided with a semiconductor substrate having a main surface, an ONO film (a laminated film of an oxide film, a nitride film and an oxide film) formed on the main surface and having a charge storage part, a pair of buried diffusion bit lines formed in the semiconductor substrate located on both sides of the ONO film, oxide films deposited on the main surface so as to cover the buried diffusion bit lines, and a transfer gate electrode formed on the ONO film.

    Abstract translation: 本发明的非挥发性半导体存储器件具有主表面，形成在主表面上的ONO膜（氧化膜层叠膜，氮化膜和氧化膜）的半导体基板，具有 电荷存储部分，形成在位于ONO膜两侧的半导体衬底中的一对掩埋扩散位线，沉积在主表面上以覆盖掩埋扩散位线的氧化膜，以及形成在 ONO电影。

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