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    MECHANISM FOR PERFORMING DISTRIBUTED POWER MANAGEMENT OF A MULTI-GPU SYSTEM
    92.
    发明申请
    MECHANISM FOR PERFORMING DISTRIBUTED POWER MANAGEMENT OF A MULTI-GPU SYSTEM 有权

    公开(公告)号：US20220091657A1

    公开(公告)日：2022-03-24

    申请号：US17031739

    申请日：2020-09-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien

    IPC: G06F1/3228 ,  G06F9/48

    Abstract: Systems, apparatuses, and methods for efficient power management of a multi-node computing system are disclosed. A computing system includes multiple nodes that receive tasks to process. The nodes include a processor, local memory, a power controller, and multiple link interfaces for transferring messages with other nodes across links. Using a distributed approach for power management, negotiation for powering down components of the computing system occurs without performing a centralized system-wide power down. Each node is able to power down its links, its processor and other components regardless of whether other components of the computing system are still active or powered up. A link interface initiates power down of a link with delay or without delay based on a prediction of whether a link idle condition leads to the link interface remaining idle for at least a target idle threshold period of time.

    LONG-IDLE STATE SYSTEM AND METHOD
    93.
    发明申请
    LONG-IDLE STATE SYSTEM AND METHOD 有权

    公开(公告)号：US20210200298A1

    公开(公告)日：2021-07-01

    申请号：US16730252

    申请日：2019-12-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander J. Branover ,  Benjamin Tsien

    IPC: G06F1/3234 ,  G06F13/16 ,  G06F9/4401 ,  G06F13/28 ,  G06F1/3296 ,  G06F1/3287

    Abstract: Methods, devices and systems for power management in a computer processing device are disclosed. The methods may include selecting, by a data fabric, D23 as target state, selecting D3 state by a memory controller, blocking memory access, reducing data fabric and memory controller clocks, reduce SoC voltage, and turning PHY voltage off. The methods may include signaling to wake up the SoC, starting exit flow by ramping up SoC voltage and ramping data fabric and memory controller clocks, unblocking memory access, propagating activity associated with the wake up event to memory, exiting D3 by PHY, and exiting self-refresh by a memory.

    METHOD OF TASK TRANSITION BETWEEN HETEROGENOUS PROCESSORS
    94.
    发明申请
    METHOD OF TASK TRANSITION BETWEEN HETEROGENOUS PROCESSORS 有权

    公开(公告)号：US20210173715A1

    公开(公告)日：2021-06-10

    申请号：US16709404

    申请日：2019-12-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander J. Branover ,  Benjamin Tsien ,  Elliot H. Mednick

    IPC: G06F9/50 ,  G06F11/30

    Abstract: A method, system, and apparatus determines that one or more tasks should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. To relocate the one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor.

    SAVE AND RESTORE SCOREBOARD
    95.
    发明申请
    SAVE AND RESTORE SCOREBOARD 审中-公开

    公开(公告)号：US20190259448A1

    公开(公告)日：2019-08-22

    申请号：US15902580

    申请日：2018-02-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Chintan S. Patel ,  Vamsi Krishna Alla ,  Alan Dodson Smith

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G06F1/3275 ,  G06F1/3287

    Abstract: Systems, apparatuses, and methods for using a scoreboard to track updates to configuration state registers are disclosed. A system includes one or more processing nodes, one or more memory devices, a plurality of configuration state registers, and a communication fabric coupled to the processing unit(s) and memory device(s). The system uses a scoreboard to track updates to the configuration state registers during run-time. Prior to a node going into a power-gated state, the system stores only those configuration state registers that have changed. This reduces the amount of data written to memory on each transition into power-gated state, and increases the amount of time the node can spend in the power-gated state. Also, configuration state registers are grouped together to match the memory access granularity, and each group of configuration state registers has a corresponding scoreboard entry.”

    MULTI-NODE SYSTEM LOW POWER MANAGEMENT
    96.
    发明申请
    MULTI-NODE SYSTEM LOW POWER MANAGEMENT 审中-公开

    公开(公告)号：US20190196574A1

    公开(公告)日：2019-06-27

    申请号：US15850261

    申请日：2017-12-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Bryan P. Broussard ,  Vydhyanathan Kalyanasundharam

    IPC: G06F1/32 ,  G06F13/26

    CPC classification number: G06F1/3296 ,  G06F1/3275 ,  G06F12/0833 ,  G06F13/26

    Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system including multiple nodes utilizes a non-uniform memory access (NUMA) architecture. A first node receives a broadcast probe from a second node. The first node spoofs a miss response for a powered down third node, which prevents the third node from waking up to respond to the broadcast probe. Prior to powering down, the third node flushed its probe filter and caches, and updated its system memory with the received dirty cache lines. The computing system includes a master node for storing interrupt priorities of the multiple cores in the computing system for arbitrated interrupts. The cores store indications of fixed interrupt identifiers for each core in the computing system. Arbitrated and fixed interrupts are handled by cores with point-to-point unicast messages, rather than broadcast messages.

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