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    Probe interrupt delivery
    1.
    发明授权
    Probe interrupt delivery 有权

    公开(公告)号：US11210246B2

    公开(公告)日：2021-12-28

    申请号：US16112367

    申请日：2018-08-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Eric Christopher Morton ,  Bryan P. Broussard ,  Paul James Moyer ,  William Louie Walker

    IPC: G06F13/24 ,  G06F13/42

    Abstract: Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

    SYSTEM-WIDE LOW POWER MANAGEMENT
    2.
    发明申请
    SYSTEM-WIDE LOW POWER MANAGEMENT 有权

    公开(公告)号：US20210333860A1

    公开(公告)日：2021-10-28

    申请号：US17366423

    申请日：2021-07-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Greggory D. Donley ,  Bryan P. Broussard

    IPC: G06F1/3287 ,  G06F9/50 ,  G06F1/3209 ,  G06F1/3234 ,  G06F1/3296

    Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system includes multiple nodes. When power down negotiation is distributed, negotiation for system-wide power down occurs within a lower level of a node hierarchy prior to negotiation for power down occurring at a higher level of the node hierarchy. When power down negotiation is centralized, a given node combines a state of its clients with indications received on its downstream link and sends an indication on an upstream link based on the combining. Only a root node sends power down requests.

    Bandwidth matched scheduler
    3.
    发明授权
    Bandwidth matched scheduler 有权

    公开(公告)号：US10601723B2

    公开(公告)日：2020-03-24

    申请号：US15951844

    申请日：2018-04-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alan Dodson Smith ,  Vydhyanathan Kalyanasundharam ,  Bryan P. Broussard ,  Greggory D. Donley ,  Chintan S. Patel

    IPC: H04L12/873 ,  H04L12/841 ,  H04L12/877 ,  H04L12/875 ,  H04L12/54 ,  H04L12/70

    Abstract: A computing system uses a memory for storing data, one or more clients for generating network traffic and a communication fabric with network switches. The network switches include centralized storage structures, rather than separate input and output storage structures. The network switches store particular metadata corresponding to received packets in a single, centralized collapsing queue where the age of the packets corresponds to a queue entry position. The payload data of the packets are stored in a separate memory, so the relatively large amount of data is not shifted during the lifetime of the packet in the network switch. The network switches select sparse queue entries in the collapsible queue, deallocate the selected queue entries, and shift remaining allocated queue entries toward a first end of the queue with a delay proportional to the radix of the network switches.

    System-wide low power management
    5.
    发明授权
    System-wide low power management 有权

    公开(公告)号：US11054887B2

    公开(公告)日：2021-07-06

    申请号：US15856546

    申请日：2017-12-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Greggory D. Donley ,  Bryan P. Broussard

    IPC: G06F1/32 ,  G06F1/3287 ,  G06F9/50 ,  G06F1/3209 ,  G06F1/3234 ,  G06F1/3296

    Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system includes multiple nodes. When power down negotiation is distributed, negotiation for system-wide power down occurs within a lower level of a node hierarchy prior to negotiation for power down occurring at a higher level of the node hierarchy. When power down negotiation is centralized, a given node combines a state of its clients with indications received on its downstream link and sends an indication on an upstream link based on the combining. Only a root node sends power down requests.

    Multi-node system low power management
    6.
    发明授权
    Multi-node system low power management 审中-公开

    公开(公告)号：US10671148B2

    公开(公告)日：2020-06-02

    申请号：US15850261

    申请日：2017-12-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Bryan P. Broussard ,  Vydhyanathan Kalyanasundharam

    IPC: G06F1/3296 ,  G06F13/26 ,  G06F12/0831 ,  G06F1/3234

    Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system including multiple nodes utilizes a non-uniform memory access (NUMA) architecture. A first node receives a broadcast probe from a second node. The first node spoofs a miss response for a powered down third node, which prevents the third node from waking up to respond to the broadcast probe. Prior to powering down, the third node flushed its probe filter and caches, and updated its system memory with the received dirty cache lines. The computing system includes a master node for storing interrupt priorities of the multiple cores in the computing system for arbitrated interrupts. The cores store indications of fixed interrupt identifiers for each core in the computing system. Arbitrated and fixed interrupts are handled by cores with point-to-point unicast messages, rather than broadcast messages.

    LINK LAYER DATA PACKING AND PACKET FLOW CONTROL SCHEME
    7.
    发明申请
    LINK LAYER DATA PACKING AND PACKET FLOW CONTROL SCHEME 审中-公开

    公开(公告)号：US20200059437A1

    公开(公告)日：2020-02-20

    申请号：US16105367

    申请日：2018-08-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Greggory D. Donley ,  Bryan P. Broussard ,  Vydhyanathan Kalyanasundharam

    IPC: H04L12/865

    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple fabric interfaces in clients and a fabric. A packet transmitter in the fabric interface includes multiple queues, each for storing packets of a respective type. The packet transmitter includes multiple queue arbiters, each for selecting a candidate packet from a respective one of the multiple queues. The packet transmitter includes a buffer for storing a link packet, which includes data storage space for storing multiple candidate packets. The packet transmitter selects qualified candidate packets from the multiple queues and inserts these candidate packets into the link packet. The packing arbiter avoids data collisions at the receiver by taking into consideration mismatches between the rate of inserting candidate packets into the link packet and the rate of creating available data storage space in a receiving queue in the receiver.

    PROBE INTERRUPT DELIVERY
    10.
    发明申请
    PROBE INTERRUPT DELIVERY 审中-公开

    公开(公告)号：US20200065275A1

    公开(公告)日：2020-02-27

    申请号：US16112367

    申请日：2018-08-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Eric Christopher Morton ,  Bryan P. Broussard ,  Paul James Moyer ,  William Louie Walker

    IPC: G06F13/24 ,  G06F13/42

    Abstract: Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

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