公开(公告)号：US20220173046A1

公开(公告)日：2022-06-02

申请号：US17210682

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Sanka Ganesan ,  Abhishek A. Sharma ,  Doug B. Ingerly ,  Mauro J. Kobrinsky ,  Kevin Fischer

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/12

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

公开(公告)号：US11342457B2

公开(公告)日：2022-05-24

申请号：US16633094

申请日：2017-09-18

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Willy Rachmady ,  Brian S. Doyle ,  Abhishek A. Sharma ,  Elijah V. Karpov ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

Abstract: Strained thin film transistors are described. In an example, an integrated circuit structure includes a strain inducing layer on an insulator layer above a substrate. A polycrystalline channel material layer is on the strain inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material.

公开(公告)号：US11335705B2

公开(公告)日：2022-05-17

申请号：US16631811

申请日：2017-09-15

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Abhishek A. Sharma ,  Elijah V. Karpov

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/78

Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.

公开(公告)号：US11335686B2

公开(公告)日：2022-05-17

申请号：US16669599

申请日：2019-10-31

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Tahir Ghani ,  Doug Ingerly ,  Rajesh Kumar

IPC: H01L27/108

Abstract: Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.

公开(公告)号：US11322620B2

公开(公告)日：2022-05-03

申请号：US16648974

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Van H. Le ,  Ashish Agrawal ,  Seung Hoon Sung ,  Abhishek A. Sharma ,  Ravi Pillarisetty

IPC: H01L29/786 ,  C30B29/08 ,  C30B29/40 ,  H01L27/088

Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

公开(公告)号：US11296087B2

公开(公告)日：2022-04-05

申请号：US16473592

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Shriram Shivaraman ,  Yih Wang ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L29/417 ,  H01L29/49 ,  H01L27/108 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US11264449B2

公开(公告)日：2022-03-01

申请号：US16828497

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Manish Chandhok ,  Abhishek A. Sharma ,  Roman Caudillo ,  Scott B. Clendenning ,  Cheyun Lin

IPC: H01L21/00 ,  H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11251227B2

公开(公告)日：2022-02-15

申请号：US16480598

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L27/22 ,  H01L27/24 ,  H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  H01L43/12 ,  H01L45/00

Abstract: A programmable array including a plurality of cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, the transistor including a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region and includes a width dimension equivalent to a width dimension of the body of the transistor. A method of forming an integrated circuit including forming bodies in a plurality rows on a substrate, each of the bodies including a programmable element and a first diffusion region, a second diffusion region and a channel of a transistor; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material; and replacing the masking material with an address line material.

公开(公告)号：US20210399113A1

公开(公告)日：2021-12-23

申请号：US17465652

申请日：2021-09-02

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Brian S. Doyle ,  Abhishek A. Sharma ,  Prashant Majhi ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey

IPC: H01L29/51 ,  H01L21/28 ,  H01L27/22 ,  H01L27/24 ,  H01L29/40 ,  H01L29/49

Abstract: A transistor, including an antiferroelectric (AFE) gate dielectric layer is described. The AFE gate dielectric layer may be crystalline and include oxygen and a dopant. The transistor further includes a gate electrode on the AFE gate dielectric layer, a source structure and a drain structure on the substrate, where the gate electrode is between the source structure and the drain structure. The transistor further includes a source contact coupled with the source structure and a drain contact coupled with the drain structure.

公开(公告)号：US11195578B2

公开(公告)日：2021-12-07

申请号：US16636904

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Brian S. Doyle ,  Elijah V. Karpov ,  Prashant Majhi

IPC: G11C13/00 ,  H01L27/24

Abstract: One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F2 or less density.