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    MICROELECTRONIC ASSEMBLIES HAVING MAGNETIC CORE INDUCTORS
    93.
    发明申请
    MICROELECTRONIC ASSEMBLIES HAVING MAGNETIC CORE INDUCTORS 审中-公开

    公开(公告)号：US20200098621A1

    公开(公告)日：2020-03-26

    申请号：US16140398

    申请日：2018-09-24

    Applicant: Intel Corporation

    Inventor： Krishna Bharath ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Kaladhar Radhakrishnan ,  Zhiguo Qian ,  Johanna M. Swan

    IPC: H01L21/768

    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.

    MICROELECTRONIC ASSEMBLIES
    94.
    发明申请
    MICROELECTRONIC ASSEMBLIES 审中-公开

    公开(公告)号：US20200091128A1

    公开(公告)日：2020-03-19

    申请号：US16161578

    申请日：2018-10-16

    Applicant: Intel Corporation

    Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Shawna M. Liff ,  Zhiguo Qian ,  Johanna M. Swan

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/532 ,  H01L23/66 ,  H01L23/538

    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.

    FAST-LANE ROUTING FOR MULTI-CHIP PACKAGES
    95.
    发明申请
    FAST-LANE ROUTING FOR MULTI-CHIP PACKAGES 审中-公开

    公开(公告)号：US20200067816A1

    公开(公告)日：2020-02-27

    申请号：US16106926

    申请日：2018-08-21

    Applicant: Intel Corporation

    Inventor： Adel A. Elsherbini ,  Tejpal Singh ,  Shawna M. Liff ,  Gerald S. Pasdast ,  Johanna M. Swan

    IPC: H04L12/733 ,  H04L12/933 ,  G06F12/0842 ,  H04L29/06

    Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.

    DISTRIBUTED ON-PACKAGE MILLIMETER-WAVE RADIO
    96.
    发明申请
    DISTRIBUTED ON-PACKAGE MILLIMETER-WAVE RADIO 审中-公开

    公开(公告)号：US20190288404A1

    公开(公告)日：2019-09-19

    申请号：US16432651

    申请日：2019-06-05

    Applicant: Intel Corporation

    Inventor： Telesphor Kamgaing ,  Adel A. Elsherbini

    IPC: H01Q21/22 ,  H01Q21/06 ,  H01Q23/00 ,  H01L23/00 ,  H01Q21/00 ,  G06K19/077

    Abstract: Embodiments described herein generally relate to phased array antenna systems or packages and techniques of making and using the systems and packages. A phased array antenna package may include a distributed phased array antenna comprising (1) a plurality of antenna sub-arrays, which may each include a plurality of antennas, (2) a plurality of Radio Frequency Dies (RFDs), each of the RFDs located proximate and electrically coupled by a trace of a plurality of traces to a corresponding antenna sub-array of the plurality of antenna sub-arrays, and (3) wherein each trace of the plurality of traces configured to electrically couple an antenna of the plurality of antennas to the RFD located proximate the antenna, wherein each trace of the plurality of traces is configured to transmit millimeter wave (mm-wave) radio signals, and wherein the plurality of traces are each of a substantially uniform length.

    MULTI-CHIP PACKAGE WITH HIGH DENSITY INTERCONNECTS
    98.
    发明申请
    MULTI-CHIP PACKAGE WITH HIGH DENSITY INTERCONNECTS 审中-公开

    公开(公告)号：US20190198447A1

    公开(公告)日：2019-06-27

    申请号：US16329644

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

    IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L25/18

    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

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