Co-support circuit panel and microelectronic packages
    93.
    发明授权
    Co-support circuit panel and microelectronic packages 有权
    支持电路板和微电子封装

    公开(公告)号:US09368477B2

    公开(公告)日:2016-06-14

    申请号:US13841052

    申请日:2013-03-15

    Abstract: A circuit panel can include contacts exposed at a connection site of a major surface thereof and configured to be coupled to terminals of a microelectronic package. The connection site can define a peripheral boundary on the major surface surrounding a group of the contacts that is configured to be coupled to a single microelectronic package. The group of contacts can include first, second, third, and fourth sets of first contacts. Signal assignments of the first and third sets of first contacts can be symmetric about a theoretical plane normal to the major surface with signal assignments of the respective second and fourth sets of first contacts. Each of the sets of first contacts can be configured to carry identical signals. Each of the sets of first contacts can be configured to carry address information sufficient to specify a location within a memory storage array of the microelectronic package.

    Abstract translation: 电路板可以包括暴露在其主表面的连接位置并被配置为耦合到微电子封装的端子的触点。 连接部位可以在被配置为耦合到单个微电子封装的一组触点周围的主表面上限定外围边界。 该组联系人可以包括第一,第二,第三和第四组第一联系人。 第一和第三组第一触点的信号分配可以相对于主表面垂直的理论平面对称,具有相应的第二和第四组第一触点的信号分配。 可以将每组第一个触点设置为携带相同的信号。 可以将每组第一触点组配置为承载足以指定微电子封装的存储器存储阵列内的位置的地址信息。

    RECONFIGURABLE PoP
    96.
    发明申请
    RECONFIGURABLE PoP 有权
    可重新配置PoP

    公开(公告)号:US20160035656A1

    公开(公告)日:2016-02-04

    申请号:US14775119

    申请日:2014-03-10

    Abstract: A microelectronic package (10) can include lower and upper package faces (11, 12), lower terminals (25) at the lower package face, upper terminals (45) at the upper package face, first and second microelectronic elements (30) each having memory storage array function, and conductive interconnects (15) each electrically connecting at least one lower terminal with at least one upper terminal. The conductive interconnects (15) can include first conductive interconnects (15a) configured to carry address in formation, signal assignments of a first set (70a) of the first interconnects having (180) rotational symmetry about a theoretical rotational axis (29) with signal assignments of a second set (70b) of first interconnects. The conductive interconnects (15) can also include second conductive interconnects (15b) configured to carry data information, the position of each second conductive interconnect having (180) rotational symmetry about the rotational axis (29) with a position of a corresponding no-connect conductive interconnect (15d).

    Abstract translation: 微电子封装(10)可以包括位于下封装面的下封装面(11,12),下端子(25),上封装面上的上端子(45),第一和第二微电子元件 具有存储器阵列功能,以及每个电连接至少一个下端子与至少一个上端子的导电互连件(15)。 导电互连(15)可以包括被配置为承载形成地址的第一导电互连(15a),具有(180)旋转对称的第一互连的第一组(70a)与理论旋转轴(29)的信号分配与信号 第一组互连(70b)的分配。 导电互连(15)还可以包括被配置为承载数据信息的第二导电互连(15b),具有(180)围绕旋转轴线(29)的(180)旋转对称的每个第二导电互连的位置具有对应的不连接 导电互连(15d)。

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