公开(公告)号：US11164969B2

公开(公告)日：2021-11-02

申请号：US15363072

申请日：2016-11-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L29/40 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L23/482 ,  H01L29/08 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.

公开(公告)号：US11094817B2

公开(公告)日：2021-08-17

申请号：US16750020

申请日：2020-01-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaoju Wu ,  Robert James Todd ,  Henry Litzmann Edwards

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L21/74 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L21/285

Abstract: A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.

公开(公告)号：US20210005599A1

公开(公告)日：2021-01-07

申请号：US17028001

申请日：2020-09-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Akram Ali Salman

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8249 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/732 ,  H01L27/082

Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.

公开(公告)号：US20200075583A1

公开(公告)日：2020-03-05

申请号：US16118648

申请日：2018-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L49/02 ,  G06F17/50

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US10529812B1

公开(公告)日：2020-01-07

申请号：US16156769

申请日：2018-10-10

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L23/528

Abstract: An integrated circuit (IC) includes a first field-plated field effect transistor (FET), and a second field-plated FET, and functional circuitry configured together with the field-plated FETs for realizing at least one circuit function in a semiconductor surface layer on a substrate. The field-plated FETs include a gate structure including a gate electrode partially over a LOCOS field relief oxide and partially over a gate dielectric layer. The LOCOS field relief oxide thickness for the first field-plated FET is thicker than the LOCOS field relief oxide thickness for the second field-plated FET. There are sources and drains on respective sides of the gate structures in the semiconductor surface layer.

公开(公告)号：US10461072B2

公开(公告)日：2019-10-29

申请号：US15895694

申请日：2018-02-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Akram A. Salman ,  Binghua Hu

IPC: H01L21/762 ,  H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/763 ,  H01L21/8222 ,  H01L27/06

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

公开(公告)号：US10269898B2

公开(公告)日：2019-04-23

申请号：US14713867

申请日：2015-05-15

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Akram A. Salman

IPC: H01L29/866 ,  H01L29/06 ,  H01L29/73 ,  H01L29/417 ,  H01L27/02

Abstract: A surrounded emitter bipolar device includes a substrate having a p-epitaxial (p-epi) layer thereon, and a p-base in the p-epi layer. A two dimensional (2D) array of p-base contacts (base units) include the p-base, wherein each base unit includes an outer dielectric structure surrounding an inner dielectric isolation ring. The inner dielectric isolation ring surrounds an n region (n+moat). A first portion of the n+moats are collector (C) units, and a second portion of the n+moats are emitter (E) units. Each of the E units is separated from a nearest neighbor E unit by a C unit.

公开(公告)号：US10177140B2

公开(公告)日：2019-01-08

申请号：US15156590

申请日：2016-05-17

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L27/102 ,  H01L27/06 ,  H01L27/02 ,  H01L21/8222 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06

Abstract: A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a lateral suppression diode. The emitter is disposed at a top surface of the transistor and configured to receive electrical current from an external source. The base is configured to conduct the electrical current from the collector to the emitter. The base is disposed at the top surface of the transistor and laterally between the emitter and the collector. The collector is configured to attract and collect minority carriers from the base. The cathode of the first conductivity type is surrounded by the base and disposed between the emitter and the collector, and the cathode is configured to suppress a lateral flow of the minority carriers from the base to the collector.

公开(公告)号：US20190006536A1

公开(公告)日：2019-01-03

申请号：US16042020

申请日：2018-07-23

Applicant: Texas Instruments Incorporated

Inventor： James Becker ,  Henry Litzmann Edwards

IPC: H01L31/0232 ,  H01L31/103 ,  H01L31/02

Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole.

公开(公告)号：US10079286B2

公开(公告)日：2018-09-18

申请号：US15472438

申请日：2017-03-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Greg Charles Baldwin

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L21/266 ,  H01L29/66 ,  H01L29/45 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L29/41758 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823475 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/092 ,  H01L27/15 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/122 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7391 ,  H01L29/7613 ,  H01L29/775 ,  H01L29/7833 ,  H01L29/7836

Abstract: Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed.