公开(公告)号：US20250147672A1

公开(公告)日：2025-05-08

申请号：US18591959

申请日：2024-02-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Y.A. ,  Sriramakrishnan Govindarajan ,  Mohd Asif Farooqui ,  Shailesh Ganapat Ghotgalkar ,  Sai Karthik Rajaraman ,  Pratheesh Gangadhar TK ,  David Smith ,  Niraj Nandan

IPC: G06F3/06

Abstract: Systems and methods for servicing read requests may include receiving a transaction from a processing unit while mirroring contents from an external memory to an on-chip RAM. Such systems and methods may monitor a progress of the mirroring and, based on the monitoring, access code or data values for the transaction from either the external memory or the on-chip RAM. Such systems and methods may further provide the code or data values to the processing unit according to the transaction. Such systems and methods may allow for execution of software before software has been fully downloaded to internal memory.

公开(公告)号：US12236562B2

公开(公告)日：2025-02-25

申请号：US18465250

申请日：2023-09-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gang Hua ,  Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody

IPC: G06T5/80 ,  G06T3/18 ,  G06T7/60 ,  G06T11/40

Abstract: A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.

公开(公告)号：US12185007B2

公开(公告)日：2024-12-31

申请号：US18091798

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Mihir Narendra Mody ,  Rajasekhar Allu

IPC: H04N25/77 ,  H04N23/698 ,  H04N23/81

Abstract: In an example, a method includes receiving image data of an input image having lines therein. The method also includes storing a first portion of the image data in a circular buffer in a first memory, wherein the first portion begins at a circular buffer start line in the input image and ends at a circular buffer end line in the input image. The method includes storing a second portion of the image data in a linear buffer in a second memory, where the second portion is non-overlapping with the first portion. The method includes processing the second portion of the image data to produce a first block of an output image. The method includes processing the first portion of the image data to produce a second block of the output image.

公开(公告)号：US12050929B2

公开(公告)日：2024-07-30

申请号：US17123653

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4812 ,  G06F9/5027 ,  G06F2209/5018

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.

公开(公告)号：US11995806B2

公开(公告)日：2024-05-28

申请号：US17080884

申请日：2020-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody ,  Gang Hua ,  Brian Okchon Chae ,  Shashank Dabral ,  Hetul Sanghvi ,  Vikram Vijayanbabu Appia ,  Sujith Shivalingappa

IPC: G06T5/80 ,  G06T3/047 ,  G06T3/18

CPC classification number: G06T5/80 ,  G06T3/047 ,  G06T3/18 ,  G06T2200/32 ,  G06T2207/10024 ,  G06T2207/20021

Abstract: A method for geometrically correcting a distorted input frame and generating an undistorted output frame includes capturing and storing an input frame in an external memory, allocating an output frame with an output frame size and dividing the output frame into output blocks, computing a size of the input blocks in the input image corresponding to each output blocks, checking if the size of the input blocks is less than the size of the internal memory and if not dividing until the required input block size of divided sub blocks is less than the size of the internal memory, programming an apparatus with input parameters, fetching the input blocks into an internal memory, processing each of the divided sub blocks sequentially and processing the next output block in step until all the output blocks are processed; and composing the output frame for each of the blocks in the output frame.

公开(公告)号：US11974062B2

公开(公告)日：2024-04-30

申请号：US17690829

申请日：2022-03-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Brijesh Jadav ,  Gang Hua ,  Niraj Nandan ,  Rajasekhar Reddy Allu ,  Ankur Ankur ,  Mayank Mangla

IPC: H04N5/262 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

CPC classification number: H04N5/2628 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.

公开(公告)号：US20240040096A1

公开(公告)日：2024-02-01

申请号：US17983905

申请日：2022-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jing-Fei Ren ,  Hrushikesh Garud ,  Rajasekhar Allu ,  Gang Hua ,  Niraj Nandan ,  Mayank Mangla ,  Mihir Narendra Mody

IPC: H04N9/64 ,  G06T7/90 ,  G06T7/00

CPC classification number: H04N9/646 ,  G06T7/90 ,  G06T7/0002 ,  G06T2207/10024 ,  G06T2207/30168

Abstract: Various embodiments disclosed herein relate to defective pixel detection and correction, and more specifically to using threshold functions based on color channels to compare pixel values to threshold values. A method is provided herein that comprises identifying a color channel of an image pixel in a frame and identifying a threshold function based at least on the color channel. The method further comprises applying the threshold function to one or more nearest-neighbor values to obtain a threshold value and determining whether a corresponding sensor pixel is defective based at least on a comparison of the image pixel to the threshold value.

公开(公告)号：US20230388661A1

公开(公告)日：2023-11-30

申请号：US18194249

申请日：2023-03-31

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajasekhar Allu ,  Manoj Koul ,  Pandy Kalimuthu ,  David Stoller

IPC: H04N23/81 ,  H04N23/84 ,  H04N23/88

CPC classification number: H04N23/81 ,  H04N23/843 ,  H04N23/88

Abstract: In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.

公开(公告)号：US20230385102A1

公开(公告)日：2023-11-30

申请号：US18175364

申请日：2023-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajasekhar Allu ,  Pandy Kalimuthu

IPC: G06F9/48 ,  G06F9/30

CPC classification number: G06F9/4881 ,  G06F9/30189 ,  G06F9/30079

Abstract: Various embodiments disclosed herein relate to hardware enabled pipeline control. In a hardware acceleration system, pipelines are configured to include a hardware enable flag that allows hardware initiation of the pipeline based on triggering of a configurable event. The pipeline can be configured to set the event that triggers the initiation of the pipeline. For example, the end of pipeline of a first pipeline may trigger the initiation of a second pipeline. Accordingly, pipelines that are configured to allow hardware enable based on a specifically configured event are not subject to the extra processing required to initiate the pipeline via software in external memory and triggered by an external controller.

公开(公告)号：US20230350819A1

公开(公告)日：2023-11-02

申请号：US18345098

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajat Sagar

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1668 ,  G06F13/28

Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.