公开(公告)号：US20140367835A1

公开(公告)日：2014-12-18

申请号：US13921174

申请日：2013-06-18

Applicant: United Microelectronics Corp.

Inventor： Ming-Te Wei ,  Po-Chao Tsao ,  Ching-Li Yang ,  Chien-Yang Chen ,  Hui-Ling Chen ,  Guan-Kai Huang

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.

Abstract translation: 提供了模具密封环。 模具密封环包括基材和从基材挤出的第一层。 第一层具有第一鳍环结构，并且第一鳍环结构的布局具有戳状形状。 此外，提供了一种用于形成模具密封环的方法。 提供具有有源区的衬底。 在衬底上形成图案化的牺牲层。 在图案化牺牲层的侧壁上形成间隔物。 图案化的牺牲层被去除。 通过使用间隔物作为掩模对衬底进行构图，从而同时形成Fin-FET的鳍结构和模密封环的第一层。

公开(公告)号：US20140349452A1

公开(公告)日：2014-11-27

申请号：US13899581

申请日：2013-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin

IPC: H01L21/8234

CPC classification number: H01L21/823468 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer.

Abstract translation: 提供一种制造半导体器件的方法。 形成第一堆叠结构和第二堆叠结构以分别覆盖第一鳍结构和第二鳍结构的一部分。 随后，通过原子层沉积工艺分别在翅片结构的侧壁上形成间隔物，间隔物的组成包括硅氮化硅。 之后，形成并蚀刻层间电介质，以露出硬掩模层。 形成掩模层以覆盖第二堆叠结构和介电层的一部分。 之后，在掩模层的覆盖下去除第一堆叠结构中的硬掩模层。 然后，第一堆叠结构中的虚设层被导电层代替。

公开(公告)号：US20140339641A1

公开(公告)日：2014-11-20

申请号：US13895367

申请日：2013-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Hong ,  Po-Chao Tsao

IPC: H01L27/088

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/6653

Abstract: A semiconductor device includes a substrate, a first fin structure, an electrical contact structure and a gate structure. The first fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. The substrate has a first region and a second region. A portion of the horizontal fin structure and the vertical fin structure are disposed in the first region, and the electrical contact structure directly covers the horizontal fin structure and the vertical fin structure within the first region. The gate structure partially overlaps the horizontal fin structure within the second region.

Abstract translation: 半导体器件包括衬底，第一鳍结构，电接触结构和栅极结构。 第一翅片结构包括沿着第一方向延伸的水平翅片结构和沿着第二方向延伸的垂直翅片结构。 衬底具有第一区域和第二区域。 水平翅片结构和垂直翅片结构的一部分设置在第一区域中，并且电接触结构直接覆盖第一区域内的水平翅片结构和垂直翅片结构。 栅极结构部分地与第二区域内的水平翅片结构重叠。

公开(公告)号：US20140327074A1

公开(公告)日：2014-11-06

申请号：US13875291

申请日：2013-05-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao

IPC: H01L27/088 ,  H01L27/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L27/0611 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/7851

Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.

Abstract translation: 半导体集成电路包括衬底，形成在衬底上的多栅极晶体管器件和形成在衬底中的n阱电阻器。 衬底包括多个第一隔离结构和至少形成在其中的第二隔离结构。 第一隔离结构的深度小于第二隔离结构的深度。 多栅晶体管器件包括多个翅片结构，并且翅片结构彼此平行并且通过第一隔离结构彼此间隔开。 n阱电阻器包括至少一个第一隔离结构。 n阱电阻器和多栅极晶体管器件通过第二隔离结构彼此电隔离。

公开(公告)号：US20140284671A1

公开(公告)日：2014-09-25

申请号：US13848736

申请日：2013-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L49/02 ,  H01L21/28 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L21/28 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1085 ,  H01L28/60 ,  H01L28/75 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66545

Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross- sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract translation: 半导体结构包括金属栅极，第二电介质层和接触插塞。 金属栅极位于基板和第一电介质层中，其中金属栅极包括具有U形横截面轮廓的功函数金属层和位于功函数金属层上的低电阻率材料。 第二电介质层位于金属栅极和第一电介质层上。 接触塞位于第二电介质层上，在第三电介质层中形成电容器。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US20140213028A1

公开(公告)日：2014-07-31

申请号：US13756464

申请日：2013-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao

IPC: H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823468 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An epitaxial process includes the following steps. A substrate including a first area and a second area is provided. A first gate and a second gate are formed respectively on the substrate of the first area and the second area. A first spacer and a second spacer are respectively formed on the substrate beside the first gate and the second gate at the same time. A first epitaxial structure is formed beside the first spacer and then a second epitaxial structure is formed beside the second spacer by the first spacer and the second spacer respectively.

Abstract translation: 外延工艺包括以下步骤。 提供了包括第一区域和第二区域的基板。 第一栅极和第二栅极分别形成在第一区域和第二区域的基板上。 第一间隔物和第二间隔物同时分别形成在第一栅极和第二栅极旁边的基板上。 在第一间隔物旁边形成第一外延结构，然后通过第一间隔物和第二间隔物分别在第二间隔物旁边形成第二外延结构。

公开(公告)号：US20140205953A1

公开(公告)日：2014-07-24

申请号：US13747421

申请日：2013-01-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Po-Chao Tsao ,  Chia-Jui Liang ,  En-Chiuan Liou

IPC: G03F7/20

CPC classification number: H01L21/0274 ,  G03F7/0035 ,  H01L21/0337

Abstract: A method for forming a semiconductor device comprises the following steps: first, a substrate is provided, a first photo-etching process is carried out with a first photomask to form at least one device structure and a plurality of compensation structures, wherein the first photomask comprises at least one device pattern and a plurality of dummy patterns. A photoresist layer is then formed on the device structure and each compensation structures; a second photo-etching process is then carried out with a second photomask to remove each compensation structure.

Abstract translation: 一种用于形成半导体器件的方法包括以下步骤：首先，提供衬底，利用第一光掩模进行第一光蚀刻工艺以形成至少一个器件结构和多个补偿结构，其中第一光掩模 包括至少一个设备图案和多个虚设图案。 然后在器件结构和每个补偿结构上形成光致抗蚀剂层; 然后用第二光掩模执行第二光蚀刻工艺以去除每个补偿结构。

公开(公告)号：US20140191358A1

公开(公告)日：2014-07-10

申请号：US13736082

申请日：2013-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 缓冲层的一部分在第一绝缘体和第二绝缘体之间接合，缓冲层的外侧壁和第一绝缘体的侧壁平整。

公开(公告)号：US20140183665A1

公开(公告)日：2014-07-03

申请号：US13728611

申请日：2012-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jung Li ,  Po-Chao Tsao

IPC: H01L29/49 ,  H01L29/78

CPC classification number: H01L29/49 ,  H01L21/02057 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution.

Abstract translation: 提供了包括栅极结构，第一间隔物和第二间隔物的半导体结构。 栅极结构形成在基板上，包括栅极材料层，设置在栅极材料层上的第一硬掩模层和设置在第一硬掩模层上的第二硬掩模层。 第一间隔件设置在栅极结构的侧壁上。 第二间隔件邻近第一间隔件设置。 第一硬掩模层的蚀刻速率，第一间隔物的蚀刻速率和第二间隔物的蚀刻速率与漂洗溶液中的第二硬掩模层的蚀刻速率基本相同并显着小于第二硬掩模层的蚀刻速率。